1Reader, 2,3Professor, 4Professor and Head 1,4Department of Pedodontics and Preventive Dentistry, Himachal Institute of Dental Sciences, Paonta Sahib, Himachal Pradesh India 2Department of Pedodontics and Preventive Dentistry, Swami Devi Dyal Hospital and Dental College, Panchkula, Haryana India 3Department of Pedodontics and Preventive Dentistry, Maharishi Markandeshwar College of Dental Scien...

The Vedic Personality Inventory was devised to assess the validity of the Vedic concept of the three gunas or modes of nature as a psychological categorization system. The sample of 619 subjects included persons of varying ages and occupations from a middle-size city in southeastern United States, and also of subscribers to a magazine focusing on Eastern-style spirituality. The original 90-item...

Convolution and Deconvolution is having wide area of application in Digital Signal Processing. Convolution helps to estimate the output of a system with arbitrary input, with knowledge of impulse response of the system. Linear systems characteristics are completely specified by the systems impulse response, as governed by the mathematics of convolution. And with the knowledge of impulse respons...

Surajit Chakraborty1, Kirtiman Syal2, Rajasri Bhattacharyya3 and Dibyajyoti Banerjee1* 1Department of Experimental Medicine and Biotechnology, PGIMER, Chandigarh-160012, India 2Department of Biophysics, Indian Institute of Science, Bangalore, India 3Department of Biotechnology, Maharishi Markandeshwar University, Mullana, Ambala, India Journal of Nutritional Health & Food Science Open Access Re...

Reversible digital technology can now start taking a more desirable direction for low dissipation of power, higher processing speeds. Here, we suggested the construction an 8-, 16-, 32-, 64-bit multiplier using carry-save adder, Kogge stone and HNFG adder with high operating speed proposed gate adder. The architecture device logic gates which are reversible be implemented Vedic multiplier. outp...

Implementing hardware support for all extensions of the RISC-V Instruction Set Architecture inside a processor would lead to avoidable area and power consumption for applications that rarely utilize a particular extension. In this paper, authors have first suggested a modified 3-stage pipeline alternative to the ZSCALE processor (32-bit) by UC Berkeley. Subsequently a hardware-accelerated appro...