Trends in CMOS technology point to an era of high-performance microprocessor design in which problems such as power consumption and cooling, deviceand chip-level variability, and hard and soft errors threaten to slow down historically established performance growth rates. One approach is to add more hardware to separately control each of these threatening technological trends. Let’s examine thi...

A recent prevailing trend in microprocessor architecture is the constant increase in chip-level parallelism. However, practical parallel processing instruction is made difficult by short-comings in existing platforms. The programming of graphics processing units (GPUs) is emerging as an effective alternative to the traditional paradigms, permitting students the chance to construct and assess pa...

This paper presents a comparison relating two different architectures dedicated for a vision system on chip. The first one implements a logarithmic CMOS imager and a microprocessor. The second involves the same processor with a CMOS retina which implements hardware operators and analog microprocessors. We have modeled two vision systems. The comparison is related to image processing speed, proc...

While microprocessor pipeline depths have increased dramatically over the last decade, they are fast approaching their optimal depth. As shown in Figure 9.6.1, the number of logic levels in modern processors is nearing 10 fanoutof-4 (FO4) inverter delay. Substantial further reductions will be undesirable due to pipeline overheads and power consumption [1]. Technology trends also show that globa...

Cache performance significantly influences the computation power of modern processors. With the trend of microprocessor design for both general use and embedded systems towards chip-multiple, cache performance becomes more important because an off-chip access is rather expensive in comparison with on-chip references. This means cache locality optimization remains a hot research area for the nex...

Network on chip is an emerging research topic nowadays in SoC (System on Chip) design. To fulfill the high-speed communication between different parts on a chip like microprocessor, memory or DSP etc., the people must develop new method and algorithm for fast interconnection between these components. At the same time, the power consumption of a chip especially from the interconnects of the chip...

It is predicted that the increase in microprocessor clock frequency will create bandwidth limitations for copper interconnects on Printed Circuit Boards (PCB) due to signal attenuation, Electromagnetic Interference (EMI) and crosstalk [1]. Optical interconnects could be a viable solution to these problems. This paper explores the potential and challenges for optical interconnects in UltraShort-...

With the wire-delay problem moving into dominance in VLSI chip design, a fundamental limitation is being revealed in performance and dependability of synchronous systems which require global clock distribution with as little skew as possible. The worst-case delay is influenced not only by design and fabrication process but also by the operating environment, e.g. the power supply voltage and tem...

This paper presents a new approach for estimating power dissipation in a high performance microprocessor chip. First, a characteristic profile (including parameters such as the cache miss rate, branch prediction miss rate, pipeline stalls, instruction mix, memory references, etc.) is extracted from application programs. Then, mixed integer linear programming and heuristic rules are used to grad...

Secure element is a microprocessor chip that provides secure environment to store the data, execute applications and communicate data external entities securely. As promising security feature, it used in various domains like IOT, automobile mobile phones. Nowadays, size of key be processed are increasing whereas processing time expected reduce. increases, between host increases. Host connected ...