The paper presents the concepts behind the "Urdhva Tiryagbhyam Sutra" and "Nikhilam Sutra" multiplication techniques. It then shows the architecture for a 16×16 Vedic multiplier module using Urdhva Tiryagbhyam Sutra. The paper then extends multiplication to 16×16 Vedic multiplier using "Nikhilam Sutra" technique. The 16×16 Vedic multiplier module using Urdhva Tiryagbhyam Sutra uses four 8×8 Ved...

This paper presents the design and implementation of signed-unsigned Modified Booth Encoding (SUMBE) multiplier. The present Modified Booth Encoding (MBE) multiplier and the Baugh-Wooley multiplier perform multiplication operation on signed numbers only. The array multiplier and Braun array multipliers perform multiplication operation on unsigned numbers only. Thus, the requisite of the modern ...

The present research is concerned with the determination of ductility, over-strength and response modification factors of coupled steel shear wall frames. Three structural models with various numbers of stories, bay width and coupling beam height were analyzed using static pushover and incremental nonlinear dynamic analyses. The ductility, over-strength and response modification factors for the...

The paper presents FPGA implementation of a spectral sharpening process suitable for speech enhancement and noise reduction algorithms for digital hearing aids. Booth and Booth Wallace multiplier is used for implementing digital signal processing algorithms in hearing aids. VHDL simulation results confirm that Booth Wallace multiplier is hardware efficient and performs faster than Booth’s multi...

Abstract—In this paper, a novel Chinese abacus multiplier is presented. The architecture of a 4-bit multiplier is demonstrated. The simulation results of our work are compared with the 4-bit Braun array multiplier. The 0.35μm and 0.18μm TSMC CMOS technologies are used in the simulation. The delay time of the abacus multiplier is at least 63% less than that of Braun array multiplier for 0.18μm t...

We designed a VLSI chip of FFT multiplier based on simple Cooly Tukey FFT using a floating-point representation with optimal data length based on an experimental error analysis. The VLSI implementation using HITACHI CMOS 0.18μm technology can perform multiplication of 2 to 2 digit hexadecimal numbers 19.7 to 34.3 times (25.7 times in average) faster than software FFT multiplier at an area cost ...

In this paper different low power 8x8 bit multipliers which are implemented with Tanner Tool v13.0 at 250MHz and 500MHz frequency with 65nm technology which is having a supply voltage 1.0v. There are different CMOS multiplier circuits are analyzed which are Array multiplier, Wallace tree multiplier, Row bypass Braun multiplier, Column bypass Braun multiplier, Row and Column bypass Braun multipl...

Digital multipliers are most widely used component in applications such as convolution, Fourier transform, discrete cosine transforms, and digital filtering. Because outturn of these applications mainly depends on multiplier speed, therefore multipliers must be designed efficiently. In the proposed architecture, a variable-latency multiplier design with novel AHL architecture and a razor flip f...

Fusion frames are an extension to frames that provide a framework for applications and providing efficient and robust information processing algorithms. In this article we study the erasure of subspaces of a fusion frame.