Scheming multipliers that are of high-speed, low power, and standard in design are of substantial research interest. By reducing the generated partial products speed of the multiplier can be increased. Several attempts have been made to decrease the number of partial products generated in a multiplication process. One of the attempt is Wallace tree multiplier. This paper aims at designing and i...

Multiple Valued Logic (MVL) has some important benefits such as increased data density, increased computational ability, reduced dynamic power dissipation Therefore with the help of Multiple Valued Logic (MVL) we have designed two quaternary multiplier architecture. The partial products in the multiplier are designed with quaternary voltage mode circuits. Each multiplier architecture is designe...

An adiabatic logic is a technique to design low power digital VLSI’s. This paper describes the design and VLSI implementation of a multiplier using a two phase drive adiabatic dynamic CMOS logic (2PADCL) circuit. Circuit operation and performance have been evaluated using a 4×4-bit 2PADCL multiplier fabricated in a 1.2 μm CMOS process. The experimental results show that the multiplier was opera...

Comparing the performance of a set of activities or organizations under uncertainty environment has been performed by means of Fuzzy Data Envelopment Analysis (FDEA) since the traditional DEA models require accurate and precise performance data. As regards a method for dealing with uncertainty environment, many researchers have introduced DEA models in fuzzy environment. Some of these models ar...

the main purpose of this paper is to define a new regular matrix by using fibonacci numbers and to investigate its matrix domain in the classical sequence spaces $ell _{p},ell _{infty },c$ and $c_{0}$, where $1leq p

Parallel rewriting of typed attributed graphs, based on the single-pushout approach extended by connection transformations, serves as the backbone of the multi-paradigm language XL, which is widely used in functional-structural plant modelling. XL allows to define instantiation rules, which enable an instancing of graphs at runtime for frequently occurring substructures, e.g., in 3-d models of ...

The digital all-pass filter is a computationally efficient signal processing building block which is quite useful in many signal pmcessing applications. In this tutorial paper we review the properties of digital all-pass filters, and provide a broad overview of the diversity of applications in digital filtering. Starting with the definition and basic properties of a scalar all-pass function, a ...

A study and comparison between current mode CMOS analog multiplier, CMOS current mode multiplier/divider and high frequency four quadrant current multiplier has been carried out in this paper. Current multiplier has been simulated in SPICE with 0.35μm, 0.5μm. Simulation have been done with supply voltage of 3.3V, 1.5V and 1.55V respectively. The simulated results show that characteristic of mul...

in this paper, we introduce $p$-semilinear transformations for linear algebras over a field ${bf f}$ of positive characteristic $p$, discuss initially the elementary properties of $p$-semilinear transformations, make use of it to give some characterizations of linear algebras over a field ${bf f}$ of positive characteristic $p$. moreover, we find a one-to-one correspondence between $p$-semiline...

We present a tool flow and results for a modelbased hardware design for FPGAs from Simulink descriptions which nicely integrates into existing environments. While current commercial tools do not exploit some high-level optimizations, we investigate the promising approach of using reusable subcircuits for folding transformations to control embedded multiplier usage and to optimize logic block us...