For flexible mapping of various task-level pipelines on a multi-core processor, the authors proposed the memory-centric network-on-chip (NoC). The memory-centric NoC manages producer–consumer data transactions between the tasks in the case of task-level pipelines are distributed over multiple processing cores. Since the memory-centric NoC manages the data transactions, it relieves burden of the...

Network-on-Chip (NoC) architectures represent a promising design paradigm to cope with increasing communication requirements in digital systems. Network-on-chip (NoC) has emerged as a vital factor that determines the performance and power consumption of many core systems. VLSI technology is to modify NOC internal router arrangements, shortest path allocation process and neighbor router estimati...

Networking has been proven in the computer system arena to be an extremely effective means of managing parallel communication flows in distributed systems. By distilling the most applicable concepts from this domain and by applying them in a way that suits the constraints of semiconductor design, Networks-on-chip (NoCs) have been proposed as the communication backbone for large-scale integrated...

We present the design and evaluation of a predictable Network-on-Chip (NoC) to interconnect processing units running multimedia applications with variable-bit-rate. The design is based on a connectionless strategy in which flits from different communication flows are interleaved in the same communication channel between routers. Each flit carries routing information used by routers to perform a...

On single silicon chip, the growing availability of number of resources is enforcing the designers to come up with mechanisms for effective and efficient management of these resources on a chip. Network-on-Chip (NoC) is used for highspeed inter-node communication inside a System-on-Chip (SoC). The routing algorithm is one of the key components in NOC architecture that decides the performance of...

In a network-on-chip (NoC) based manycore architecture, an offchip data access (main memory access) needs to travel through the on-chip network, spending considerable amount of time within the chip (in addition to the memory access latency). In addition, it contends with on-chip (cache) accesses as both use the same NoC resources. In this paper, focusing on data-parallel, multithreaded applicat...

Abstract The needs of the chip are growing on a daily basis as extremely large size integrated circuits evolve fast. As result, network-on-chip (NoC) was suggested and successfully developed to address issue communication on-chip. Current research focuses NoC topology routing algorithms that have substantial influence network performance. Because low power is priority, Mesh-of-Tree (MoT) archit...

This paper presents a framework for high-level exploration and RTL design of an optimized Network-on-Chip (NoC) architecture for 3D chips. The RTL is derived from the high-level exploration methodology in a semi-automated way. FPGA implementation figures are given for various implementation parameters of the Network Interface Element, demonstrating the performance/area trade-off of 3D NoC archi...

Study of Network-on-Chip (NoC) systems requires simulators capable of handling their unique characteristics. Toward this objective, a set of simulation models are developed based on NoC first principles and the DEVS framework. The components necessary to build simulation models for NoC are developed using Parallel DEVS and implemented in NoC-DEVS which extends the generalpurpose DEVS-Suite simu...

Network-on-chip-based multiprocessor systems-on-chip (NoC-based MP-SoCs) are considered as future embedded systems platforms. One of the steps in mapping an application onto such a parallel platform involves determining when data is sent between the tasks in the application. As a network-on-chip allows concurrent communication, a decision on the route through the network must also be made. Timi...