We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer sizing and wire sizing problem. We propose a simple buffering architecture for this problem and show that this architecture achieves a near optimal solution. We also derive simple models for a buffered wire which are suit...

In this paper, we study wire width planning for interconnect performance optimization in an interconnect-centric design flow. We first propose some simplified, yet near-optimal wire sizing schemes, using only one or two discrete wire widths. Our sensitivity study on wire sizing optimization further suggests that there exists a small set of “globally” optimal wire widths for a range of interconn...

Power loss and voltage uncertainty are the major issues prevalently faced in design of distribution systems. But such can be resolved through effective usage networking reconfiguration that has a combination Distributed Generation (DG) units from networks. In this point view, optimal placement sizing DGs ways to boost performance power The optimum allocation resolves various problems namely, lo...