We present an efficient new method of obtaining a generator matrix G from certain types of parity check matrices with a defective cyclic block structure. This novel approach describes parity check and generator matrices in terms of polynomials. Moreover, by using this polynomial algebra we have found efficient ways to implement the scheme. In addition, this method is as such interesting as it a...

An algorithm for constructing parity-check matrices of nonbinary quasi-cyclic low-density parity-check (NB QC-LDPC) codes is proposed. The algorithm finds short cycles in the base matrix and tries to eliminate them by selecting the circulants and the elements of GF(q). Firstly the algorithm tries to eliminate the cycles with the smallest number edges going outside the cycle. The efficiency of t...

A Low Density Parity Check iterative decoder is implemented in 0.13 μm CMOS technology with 6 metal layers. Using a 1023 x 32 parity-check matrix, this code has at least an order of magnitude less computational requirement than traditional error correcting methods that provide similar bit-error rate performance. Power and throughput optimization is achieved through exploitation of massive amoun...

The correspondence gives a new condition for a -ary linear code of length and minimum distance to be extendable to a code of the same dimension, length + 1, and minimum distance

Low-density parity-check (LDPC) codes are very powerful error-correction codes with capabilities approaching the Shannon’s limits. In evaluating the error performance of a LDPC code, the computer simulation time taken becomes a primary concern when tens of millions of noise-corrupted codewords are to be decoded, particularly for codes with very long lengths. In this paper, we propose modeling t...

The concept of parity check matrices of linear binary codes has been extended by Heden [9] to parity check systems of nonlinear binary codes. In the present paper we extend this concept to parity check systems of nonlinear codes over finite commutative Frobenius rings. Using parity check systems, results on how to get some fundamental properties of the codes are given. Moreover, parity check sy...

The approach proposed in this paper reduces power consumption in single-error correcting, double error-detecting checker circuits that perform memory ECC. Power is minimized with little or no impact on area and delay, using the degrees of freedom in selecting the parity check matrix of the error correcting code. The non-linear power optimization problem is solved using two methods, genetic algo...

This paper is concerned with general analysis on the rank and row-redundancy of an array of circulants whose null space defines a QC-LDPC code. Based on the Fourier transform and the properties of conjugacy classes and Hadamard products of matrices, we derive tight upper bounds on rank and row-redundancy for general array of circulants, which make it possible to consider row-redundancy in const...

The key step of generating the well-known Hsiao code is to construct a {0, 1}-check-matrix in which each column contains the same odd-number of 1’s and each row contains the same number of 1’s or differs at most by one for the number of 1’s. We also require that no two columns are identical in the matrix. The author solved this problem in 1986 by introducing a type of recursively balanced matri...