This paper describes the different logic style used for CMOS full adders and different equation used to implement the required Boolean logic for full adders. This paper also describes that the speed of the design is limited by size of the transistors, parasitic capacitance and delay in the critical path. Power consumption and speed are two important but conflicting design aspects; hence a bette...

Performance of high fan–in Domino circuits is degraded by technology scaling due to exponential increase in leakage. To improve the performance Current Comparison Domino (CCD) circuits are widely used. This work presents design of wide fan-in high performance current comparison domino circuits with goals of minimizing the power dissipation and propagation delay at 90nm and 45nm ultra deep submi...

Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. Domino logic overcomes the difficulties in dynamic circuits such as charge sharing and cascading. In this paper we are proposing a wide fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the ch...

High speed Full-Adder (FA) module is an important element in designing high performance arithmetic circuits. In this paper, I propose a high speed multiple-valued logic FA module. The proposed FA is designed and constructed with the use of 3 capacitors and 14 transistors, wh e r e t h e t r a n s i s t or s a r e c o n s t r u c t e d b y carbon nano-tube field effect transistor (CNFET) technol...

In this presented work we designed the 4- bit Arithmetic & Logical Unit (ALU) by using different modules. The Various modules are AND gate OR with six transistors, While XOR is both eight transistors transistors. transistor module gives optimized results. Another one four multiplexer implemented Pass logic (PTL) style. full adder 18 through PTL Here because of style number count such that c...

A binary comparator architecture is proposed in this work for static logic to achieve both low-power and high-performance operations. It also presents a detailed timing performance power analysis of various state-of-the-art designs. The main advantages design are its high speed efficiency maintained over wide range operands size, which useful at low-input data activity environments. circuit use...

This paper presents the least-mean-square (LMS) adaptive filter for deriving its Architectures for high-speed and low complexity implementation. It is shown that the direct-form LMS adaptive filter has nearly the same critical path as its transpose-form counterpart, but provides much faster convergence and lower register complexity. From the critical-path evaluation, it is further shown that no...

Field Programmable Gate Array (FPGA) attributes of logic configurability, bitstream storage, and dynamic signal routing can be realized by leveraging the complementary benefits of emerging devices with Complementary Metal Oxide Semiconductor (CMOS)-based devices. In this paper, a novel Carbon/Magnet Lookup Table (CM-LUT) is developed and evaluated by trading off a range of mixed heterogeneous t...

In this paper propose a new high performance 1 bit full adder cell using XOR/XNOR gate design style as well as lower power consumption. Simulation results illustrate the superiority of the resulting proposed adder against conventional 1-bit full-adder in terms of power consumption improvement performance (98% of 10T, 47% of 14T & 16T), propagation delay and PDP. We have performed simulations us...