The paper presents a study on the impact of using SIMD (Singe Instruction Multiple Data) techniques and architectures in low level image processing. Speedups obtained on a SIMD parallel architecture (IMAPVISION board) and a single Intel MMX processor computer are presented for different low-level image processing operators. While the IMAP-Vision system performs better because of the large numbe...

indubitably, the efficacy of metalinguistic awareness in improving efl learners’ grammatical knowledge and writing quality has long been an area of great interest in applied linguistics brown (2001). accordingly, the main objective of the present study was to investigate the impact of planned and unplanned focus on form instruction on students’ ability to learn grammar and use it appropriately ...

Current microprocessors utilise the instruction-level parallelism by a deep processor pipeline and the superscalar instruction issue technique. VLSI technology offers several solutions for aggressive exploitation of the instruction-level parallelism in future generations of microprocessors. Technological advances will replace the gate delay by on-chip wire delay as the main obstacle to increase...

Taking advantage of instruction level parallelism is one of the key factors in improving computer performance. The main performance inhibitor in a pipelined processor is the branch penalty. Many techniques have been developed to reduce this penalty. The technique of branch prediction was explored further. Branch predictors are crucial in today's modern, superscalar processors for achieving high...

Modern trends in mobile and embedded devices require ever increasing levels of performance, while maintaining low power consumption and silicon area usage. This thesis presents a new architecture for a high-performance embedded processor, based upon the instruction-level distributed processing (ILDP) methodology. A qualitative analysis of the complexity of an ILDP implementation as compared to ...

Efficient implementation of block ciphers is critical towards achieving both high security and high-speed processing. Numerous block ciphers have been proposed and implemented, using a wide and varied range of functional operations. As a result, it has become increasingly more difficult to develop a hardware architecture that allows the efficient and fast realization of a wide variety of block ...

Within two or three technology generations, processor architects will face a number of major challenges. Wire delays will become critical, and power considerations will temper the availability of billions of transistors. Many important applications will be object-oriented, multithreaded, and will consist of many separately compiled and dynamically linked parts. To accommodate these shifts in bo...

For too long a time, how to memorize more words and keep them longer in mind has been a primary and everlasting problem for vocabulary teaching and learning. This study focused on deep processing as a word memorizing strategy in contextualizing, deand recontextualizing learning stages. It also examined possible effects of such pedagogy on vocabulary competence and attitude towards word learning...

This study synthesizes 79 standardized mean-change differences between control and treatment groups from 17 independent studies, investigating the effect of morphological interventions on literacy outcomes for students with literacy difficulties. Average total sample size ranged from 15 to 261 from a wide range of grade levels. Overall, morphological instruction showed a significant improvement...