The Wallace Multiplier is mainly used in the Arithmetic & Logic Unit (ALU) to perform the scientific computation in processors, controller etc... The existing multiplication technique like booth multiplier, array multiplier etc requires more time in multiplications. Hence Wallace Multiplier has been designed by using the parallel process to reduce the delay. The regular Wallace Multiplier requi...

A specifically designed aza-starphene molecule is presented where contacting one, two, and/or three single Al adatoms allows this to function as a “3-inputs & 2-outputs” digital full adder on Au(111) surface. Sequentially positioning with atomic precision interact aza-starphene, inputs one classical digit per Al, which converted quantum information by the molecule. The intramolecular logical ca...

This paper analyzes the effect of random phase shifts in the underlying clock signals on the operation of several basic Quantum-dot Cellular Automata (QCA) building blocks. Such phase shifts can result from manufacturing variations or from uneven path lengths in the clocking network. We perform numerical simulations of basic building blocks using two different simulation engines available in th...

The overall view of this paper is to attain high speed, low power full adder cells with alternative logic cells that lead to have reduced power delay product. Two high-speed and low-power full adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-add...

Reversible quantum computer is gaining interest for the future computer system. With the advent of quantum computer and reversible logic, design and implementation of all devices has received more attention. BCD digit adder is the basic unit of the more precise decimal computer arithmetic. The research objective is to increase speed of operation for addition of BCD numbers while minimizing the ...

This paper presents a new early output hybrid input encoded asynchronous full adder designed using dual-rail and 1-of-4 delay-insensitive data codes. The proposed full adder when cascaded to form a ripple carry adder (RCA) necessitates the use of a small relative-timing assumption with respect to the internal carries, which is independent of the RCA size. The forward latency of the proposed hyb...

In this paper we present a 1 bit Full Adder Cell. It was implemented with lesser number of transistors and lesser power consumption compared to the existing implementations of the Full Adder. Simulations are carried for supply voltages of 1.2v, 0.8v in HSPICE at 0.18μmCMOS technology. Proposed Full Adder results show that there was a reduction of power consumption and efficient in area. Area wa...