In this paper, we introduce design models for Totally Self Checking, Code Disjoint (T S C / C D) and Strongly Fault Secure, Strongly Code Disjoint (SFS/SCDJ synchronous controllers. The T S C / C D and SF / S C D models based on two new proposed low-cost, modular, Totally Self Checking (TSC), edge triggered and error propagating (code disjoint) Flip-Flops; one, a D Flip-Flop which can be used i...

Flip-flops and latches are the most important elements of a design for both a delay and energy point of view. In many electronics design low power consumption is basic need in most of the applications. The energy performance requirements enhance the most designers of next generation system towards the least possible power consumption. The power consumption is basically reduced by scaling of a p...

Gene regulatory networks (GRNs) form naturally predefined and optimised computational units envisioned to act as biohardware able to solve hard computational problems efficiently. This interplay of GRNs via signalling pathways allows the consideration as well as implementation of interconnection-free and fault tolerant programmable computing agents. It has been quantitatively shown in an in viv...

Glutamate-activated α-amino-3-hydroxy-5-methyl-4-isoxazolepropionic acid receptors (AMPA-Rs) mediate the majority of excitatory neurotransmission in brain and thus are major drug targets for diseases associated with hyperexcitability or neurotoxicity. Due to the critical nature of AMPA-Rs in normal brain function, typical AMPA-R antagonists have deleterious effects on cognition and motor functi...

Memory elements play a vital role on Digital World. In memory devices the most important factor is power consumption. Because the power consumption of the memory device increases means, the device reliability and life time is reduced. The basic memory elements of designer considerations are Latch and Flip-flop. In this paper we design SRAM using arrays of flip-flops and we analyze the design of...

Flip-flops are critical timing elements in digital circuits which have a large impact on circuit speed and power consumption in VLSI circuits. In this paper, a dualedge triggered flip-flop with high performance and clock gated sense amplifier flip-flop is designed. Moreover, the pulse generator can be shared among many flip-flops to reduce the power dissipation and chip area. By incorporating t...

ABSTRACT: All-optical T (Toggle) flip-flop with preset (PR) and clear (CLR) are basic building modules for the development of ultra-high speed all optical binary counter. In this paper, a non-linear material based alloptical switching mechanism is utilized here to realize the all-optical T flip-flop with PR and CLR. A composite slab of linear medium (LM) and non-linear medium (NLM) is used to d...

The dynamic behavior of surface dimers on Ge(001) has been studied by positioning the tip of a scanning tunneling microscope over single flip-flopping dimers and measuring the tunneling current as a function of time. We observe that not just symmetric, but also asymmetric appearing dimers exhibit flip-flop motion. The dynamics of flip-flopping dimers can be used to sensitively gauge the local p...

As the density and operating speed of CMOS VLSI chips increases, leakage power dissipation becomes more and more significant. This paper presents a leakage power behavior in Pulse triggered flip-flop. All the designs are simulated with and without the application of leakage reduction techniques and the readings are presented. By analyzing the leakage path of flip flops we propose a method to re...