Integrated circuit (IC) camouflaging is a promising technique to protect the design of a chip from reverse engineering. However, recent work has shown that even camouflaged ICs can be reverse engineered from the observed input/output behaviour of a chip using SAT solvers. However, these so-called SAT attacks have so far targeted only camouflaged combinational circuits. For camouflaged sequentia...

We develop a method for non-trivially restricting fanout in a circuit. We study the complexity of the Circuit Value problem and a new problem, Network Stability, when fanout is limited. This leads to new classes of problems within P. We conjecture that the new classes are different from P and incomparable to JVC. One of these classes, CC, contains several natural complete problems, including Ci...

Field Programmable Gate Arrays (FPGAs) are used to embed a circuit designed by users instantly. Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs). Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations. Howe...

It is known that a class of acyclic sequential circuits called balanced circuits can be tested by combinational ATPG. The first contribution of this paper is a modified and efficient combinational single fault ATPG method for any general (not necessarily balanced) acyclic circuit. Without inserting real hardware, we create a “balanced” ATPG model of the circuit in which all reconverging paths h...

In high-level synthesis, parallelization for nested loop kernels has been hard due to their complex data dependencies, especially non-uniform dependencies. In this paper, we propose a new method to synthesize a parallelized circuit from such kernels using polyhedral optimization, which has been vigorously studied in the software field. The key point of our contribution is a buffering method for...

A method for the realization of fail-safe sequential circuits is presented where flip-flops are employed for representing the internal states. First, such a design technique where the circuit will be trapped in an erroneous state into which it is transferred by a fault is shown. Further, the condition for assuring that the circuit will be dropped into the particular (predetermined) final state ...

A mixed-signal circuit that can emulate multi-layer perceptron neural networks is presented. The sequential processing provides a tradeoff between speed, power consumption and circuit area, allowing a flexible accommodation of different network structures. The design of the three most critical analog basic blocks of the processor is presented. a) Dynamic analog memories: A technique of switchin...

In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design which adopts gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals, then a clocked CMOS gate structure is presented. The PSPICE simulations demonstrate the low power characteristic of clocked CMO...

In this paper we propose an algorithm, implemented with VHDL language in RTL design, capable of reorganizing the f1ip-flops from within a circuit in order to reduce the power consumption through optimal c10ck distribution. Practically in the end, starting from this algoritbm, we will model the clock bebavior in a sequential circuit. Experimental results show tbat these designs have ideal logic ...

A restricted case of the Circuit Value Problem known as the Sequential NOR Circuit Value Problem was recently used to obtain very succinct examples of conjunctive grammars, Boolean grammars and language equations representing P-complete languages (Okhotin, “A simple P-complete problem and its representations by language equations”, MCU 2007). In this paper, a new encoding of the same problem is...