One of the most di cult aspects of experimental recon gurable architecture or CAD tool research is obtaining su ciently large benchmark circuits. One approach to obtaining such circuits is to generate them stochastically. Current circuit generators construct combinational and sequential logic circuits. Many of today's devices, however, are being used to implement entire systems, and often these...

This paper presents a new approach to test pattern generation for sequential circuits modeled as finite state machines. Based on a functional fault model, only a restricted set of transitions of the finite state machine (FSM) is considered for the purpose of testing. A new state discriminating sequence, referred to as EUIO is proposed. Overlapping is accomplished to reduce the test length. In m...

Innovative synthesis for testability strategies aim at considering testability while synthesizing a circuit, whereas conventional design for testability methods modify the design after the circuit structure is synthesized. We describe a synthesis approach that maps a behavioral FSM description into a testable gate-level structure. The term “testable” in this context, besides implying the existe...

Efficient diagnosis of faults in VLSI circuits requires high quality diagnostic test sets. In this work, novel techniques for diagnostic test generation are proposed that require significantly less time than previous methods. The set of fault pairs left undistinguished by a detection-oriented test set is first filtered to target only testable faults. Then diagnostic test generation is performed...

Recently developed methods for power estimation have primarily focused on combinational logic We present a framework for the e cient and accurate estimation of average power dissi pation in sequential circuits Switching activity is the primary cause of power dissipation in CMOS circuits Accurate switching activity estimation for sequential circuits is considerably more di cult than that for com...

AbJlraCf-The COnctpl of I p~ud~){hauSlj\'t Itsl for sequenti,l circuil, is Introduced in a .... 11.)' similar Illlha\ .. -hieh is used rur combinational net,,'urks. Using partial sun all qcJa in the dllla How or a selluentl,1 circuit art' rfmOI'ed, such Ihall compact combinational model clln be conSlrucled. Pseudot'XhIlLlSlivf tf!\1 nquences for the original circuit are constructed from • pseod...

The ever-increasing complexity and size of current circuit designs have made testing and verification major bottlenecks in the design flow of VLSI (Very Large Scale Integrated) circuits. Statistics show that more than 70% of the design effort can be spent on functional verification and manufacturing testing. This percentage is expected to increase in the future if no significant strides in thes...

This paper presents a methodology for automatic generation of massive parallel simulation systems to estimate the power consumption of sequential CMOS circuits. Based on a high level description of Finite State Machines C++ simulator code is being generated to estimate the power consumption of a CMOS based implementation. From a symbolic FSM description, a Monte Carlo simulation is used to esti...

The FPGA technology mapping and synthesis problem for combinational circuits has been well studied. But for sequential circuits, most of the previous synthesis and mapping algorithms assume that the positions of ippops are xed and synthesize each combinational block independently. Retiming is a technique to reduce the clock period by repositioning ippops LeSa91]. With retiming, the previous map...

By analyzing the working characteristics of binary Schmitt circuits we find their sequential characteristics, which makes us follow the method of sequential circuits to design Schmitt circuits. The sequential design technique is extended to the study of ternary Schmitt circuits in this paper. The designed ternary Schmitt trigger has a similar structure with a ternary flip-flop. PSPICE simulatio...