نتایج جستجو برای: settling
تعداد نتایج: 6583 فیلتر نتایج به سال:
Reducing the locking time or settling time is one of the major challenges in the design of Delay Locked Loop (DLL) based frequency synthesizer. In this paper a common structure for DLL based frequency synthesizer is considered in which the number of delay cells in the direct path is specified. Then, the designed delay locked loop is optimized using genetic algorithm (GA). GA changes the phase-v...
In this paper, an EOQ model is developed for a deteriorating item with quadratic time dependent demand rate under trade credit. Mathematical models are also derived under two different situations i.e. Case I; the credit period is less than the cycle time for settling the account and Case II; the credit period is greater than or equal to the cycle time for settling the account. The numerical exa...
The DC open-loop voltage Gain is a very important specification for amplifiers. In order to increase this specification, in this paper, we have proposed an improved folded cascode gain boosted amplifier (improved FCGBA) which has extremely large DC open-loop voltage gain. Compared to traditional FCGBA, this novel structure needs only one auxiliary amplifier, so it is energy saving. Finally, wit...
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