An arithmetic or with-carry analog of Blahut’s theorem is presented. This relates the length of the smallest feedback with carry shift register to the number of nonzero classical Fourier coefficients of a periodic binary sequence.

Rakaposhi is a synchronous stream cipher, which uses three main components a non-linear feedback shift register (NLFSR), a dynamic linear feedback shift register (DLFSR) and a non-linear filtering function (NLF ). NLFSR consists of 128 bits and is initialised by the secret key K. DLFSR holds 192 bits and is initialised by an initial vector (IV ). NLF takes 8-bit inputs and returns a single outp...

As the CMOS technology is scaling down, leakage power has become one of the most critical design concerns for the chip designer. This paper proposes a low leakage linear feedback shift register that can be used in a crypto-processor. In this work, three bit, four bit and five bit linear feedback shift registers are implemented in 90nm and 65nm technology . This paper also proposes two leakage r...

The aim of testing of VLSI circuits is high-quality screening of the circuits by targeting performance related faults. A low hardware overhead test pattern generator (TPG) for scan based BIST that can detect the any faults in the circuit under test and analyze their response .It is a new fault coverage test pattern generator using a liner feedback shift register (LFSR) called FC-LFSR can perfor...

Let x be an m-sequence, a maximal length sequence produced by a linear feedback shift register. We show that the nondeterministic automatic complexity AN (x) is close to maximal: n/2 − AN (x) = O(log 2 n), whereas Hyde has shown AN (y) ≤ n/2 + 1 for all sequences y.

Power dissipation is a challenging problem in current VLSI designs. In general the power consumption of device is more in the testing mode than in the normal system operation. Built in self test (BIST) and scan-based BIST are the techniques used for testing and detecting the faulty components in the VLSI circuit. Linear Feedback Shift Register (LFSR) in BIST generates pseudo-random patterns for...

The Mersenne Twister is a 623-dimensionally equidistributed variant of the twisted generalized feedback shift register operating in 623 dimensions [6]. It is quite fast and produces a sequence of pseudo-random numbers with an enormous period and uniform distribution, which makes it suitable for use in simulations. However, the Mersenne twister is not suitable for cryptographic use: by analyzing...

| Wireless medium is inherently insecure due to its broadcast characteristics. As wireless communications become more prevalent and utilize the radio channel for transmission of critical information, the concern for security becomes an important issue. In this paper a new CDMA-based multiple access scheme for wireless LANs is proposed to provide enhanced security. Although most of the e orts in...

In order to ensure a high product quality some authors propose pseudo-exhaustive or verification testing. This is applicable if each primary output of the combinational circuit only depends on a small set of primary inputs, where all possible patterns can be enumerated completely. But in CMOS-circuits even a single stuck-open fault may fail to be detected this way, and the already proposed addi...

Conclusions: A completely integrated silicon PRBS generator providing adjustable bit rates up to 25Gbitis is presented; 26Gbit/s are also available with a slightly degraded performance. For the first time, this bit rate is achieved by on-chip multiplexing using only one shift register and one additional Boolean operation. Furthermore, this work demonstrates the ability to realise complex integr...