The formation of boron interstitial clusters is a key limiting factor for the fabrication of highly conductive ultrashallow doped regions in future silicon-based device technology. Optimized vacancy engineering strongly reduces boron clustering, enabling low-temperature electrical activation to levels rivalling what can be achieved with conventional preamorphization and solid-phase epitaxial re...

MOS Technology on massive substrate played a critical task during micro-electronic evolution. The regular reduction of transistors sizes leads today to nanometric devices. With this reduction, some parasitic physical effects, previously with no importance, became mostly amplified, leading to the end of MOSFETs technology on massive substrate. SOI technology gives a good alternative to that mini...

Reverse-biased silicon p-n junction arrays using Silicon-On-Insulator technology have been proposed as microdosimeters. The performance of such detectors in boron neutron capture therapy (BNCT) is discussed. This work provides the first reported measurements using boron-coated silicon diode arrays as microdosimeters in BNCT. Results are in good agreement with measurements with gas proportional ...

We demonstrate a silicon photonic platform using thin buried oxide silicon-on-insulator (SOI) substrates using localized substrate removal. We show high confinement silicon strip waveguides, micro-ring resonators and nanotapers using this technology. Propagation losses for the waveguides using the cutback method are 3.88 dB/cm for the quasi-TE mode and 5.06 dB/cm for the quasi-TM mode. Ring res...

We investigate experimentally metal-insulator-silicon-insulator-metal (MISIM) waveguides that are fabricated by using fully standard CMOS technology. They are hybrid plasmonic waveguides, and they have a feature that their insulator is replaceable with functional material. We explain a fabrication process for them and discuss fabrication results based on 8-inch silicon-on-insulator wafers. We m...

Impact ionization in fully depleted (FD) Silicon On Insulator (SOI) n-Channel MOSFET is investigated as a function of the doping concentration. We have found that impact ionization increases with the decrease in the doping concentration and vice versa. Simulation results obtained from Sentaurus TCAD with the higher doping concentration can control the threshold voltage (Vth). Furthermore we hav...

We show by Monte Carlo simulation that electron mobility is greater when strained-silicon inversion layers are grown on SiGe-on-insulator substrates than when unstrained-silicon-on-insulator devices are employed ~as experimentally observed!. However, the electron mobility in strained-Si/SiGe-on-insulator inversion layers is strongly dependent on the strained-silicon layer thickness, TSi , due t...

Transistor size is decreasing day by day, therefore it is difficult to overcome the problem of short channel effects. For preventing short channel effects, source/drain engineering, substrate engineering & gate engineering have been introduced. According to chronological growth of VLSI Design, there is need of non-conventional structure of MOSFET and researchers are getting shifted in search of...

Abstarct The work presents the newly deploying technology in semiconductor industry called silicon on insulator (SOI). Its two technology partially and fully depleted SOI and describe how these are different from conventional bulk MOS technology, advantages over bulk technology and floating body effect of PD/FD SOI technology, factors effecting floating body such as kink effects in PD SOI, para...

A new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed. It is intended for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used because it provides a good compromise between speed and power consumption. The synthesis procedure is based on the relation bet...