The industrial application of formal methods and in particular of software verification tools, e.g. based on satisfiability checking and symbolic computation as being in the main focus of the SC network, necessitates two main requirements. The methods and tools, first, need to actually aim at the problem class that occur in practice and, second, have to guarantee a high level of confidence. In ...

Dear Reader, This is the second issue of the MoVES newsletter. MoVES stands for “Modelling, Verification and Evolution of Software” and addresses these fundamental issues in software engineering. The project is sponsored by the Belgian government (belspo IAP programme). Each issue of the newsletter presents a partner and a work package. This issue presents results and ongoing research ofWork Pa...

Name Abbr. Type Papers (2014) Software Testing, Verification and Reliability STVR journal 24 / year International Conference on Software Testing, Verification and Validation ICST conf. 141 submitted 40 accepted International Symposium on Software Testing and Analysis ISSTA conf. 128 submitted 36 accepted International Conference on Testing Software and Systems ICTSS conf. 36 submitted 17 accept...

This report describes the definitions, rules, setup, procedure, and results of the 1st International Competition on Software Verification. The verification community has performed competitions in various areas in the past, and SV-COMP’12 is the first competition of verification tools that take software programs as input and run a fully automatic verification of a given safety property. This yea...

ble-chip (SOPC) design becomes the norm, hardware, software, and systems designers grapple with new verification challenges in addition to the urgency of the usual time to market, cost, and performance goals. Verification is historically the longest and most critical portion of system-level design. To ease those verification blues, engineers can now power up with a comprehensive, multi-faceted ...

In this thesis, we report of a case study on feature-aware verification. Featureaware verification is the formal verification of a feature-oriented software system on a feature-modular basis. Feature-modular verification means, that specifications are assigned to a particular feature and use feature-local knowledge only. That concerns the features’ awareness of other features in a particular pr...

Verifying a complex SoC is challenging. The testbench and testcases must be developed early as these are used for everything from SoC verification to achieve higher coverage on features/protocol coverage, i/f integration and performance verification. Time to market makes early software development a necessity. Verification assisted with early software development needs more than dynamic simulat...

Formal specification and verification of software have made small but continuous advances throughout its long history, and have reached a point where commercial tools became available for verifying programs semi-automatically or automatically. The aim of the master thesis is to evaluate commercial and academic verification tools with respect to their usability in developing software and in teac...

Verification is increasingly becoming a bottleneck in the design of embedded systems and system-on-chips. In order to ensure the correctness, verification has to be performed not only on hardware, but also on software. Model checking is a promising verification technique, but suffers from the state explosion problem, which is even further exacerbated in the context of software verification main...

UML is a standard language used in business modeling for specifying, visualizing and constructing artifact for software and non software systems. It provides the capability to explore the static structure as well as dynamic behaviour of any large and complex software system. It consists of different software design patterns, templates and frameworks with unique diagrams to represent different a...