The notion of quantum-dot cellular automata (QCA) as a possible replacement paradigm for conventional transistor-based logic is reviewed. Experiments using metal tunnel structures demonstrating a functional QCA cell are presented. It is shown that single electron tunnelling transistors used as electrometers verify proper switching of the QCA cell. Additionally, we provide evidence for a QCA cel...

The switching waveforms of a series of power MOSFET devices called Logic Level FETs (L2FETs) and featuring a 5V gate drive are presented and contrasted with those of the more conventional 10V gate drive devices. A new method of characterizing MOSFET switching performance is discussed in which the MOSFET is treated as a vertical JFET driven in cascade from a low voltage lateral MOS. The 2:1 adva...

Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be reduced. An improvement in the application of this principle for multi-output circuits is presented. Techniques that trade area for power reduction and a method for minimizing the overall circuit switching probability ar...

We show that in nanoscale two-terminal resistive switches the resistance switching can be dominated by the formation of a single conductive filament. The probabilistic filament formation process strongly affects the device operation principle, and can be programmed to facilitate new functionalities such as multibit switching with partially formed filaments. In addition, the nanoscale switches e...

Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. This paper proposes a wide fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other circuits. The design also offers very...

In this paper we address the problem of minimization of power consumption in combinational circuits by minimizing the number of switching transitions at the output nodes of each gate. A powerful combinational logic optimization method using k-map is presented here that is based on disjoint implicants (implicates) of a function. More than 10% reduction in switching activity has been obtained wit...

<span lang="EN-US">This research provides a new control technique for mitigating conducted electromagnetic interference (EMI) in buck converter designed solar applications. Indeed, hard-switching direct current to (DC-DC) converters, commonly used industrial applications, pose significant risk the surrounding environment regarding compatibility (EMC). Usually, fast-switching phase induces...

As transistor switching speed improves, synchronizing a global clock increasingly degrades system performance. Therefore, self-timed asynchronous logic becomes potentially faster than synchronous logic. To do so, however, it must exploit the techniques used in fast synchronous designs, including: redundant logic, inverting logic, transistor size optimization, dynamic logic, and phase alignment....