In this proposal, we briefly outline some of the major challenges facing the adoption of Formal Verification techniques. We focus on the model checking approach, which is completely automated in principle and quite automated in practice. These challenges include handling the state explosion problem associated with large industrial designs, which manifests itself as large representation sizes an...

— In this paper, the task of recognizing signs made by hearing impaired people at sentence level has been addressed. A novel method of extracting spatial features to capture hand movements of a signer has been proposed. Frames of a given video of a sign are preprocessed to extract face and hand components of a signer. The local centroids of the extracted components along with the global centroi...

This paper presents an extensible framework for optimizing analog lter designs for multiple behavioral and implementation properties. We demonstrate the framework using the behavioral properties of magnitude response, phase response, and peak overshoot, and the implementation property of quality factors. We represent the analog lter in terms of its poles and zeroes. We match the constrained non...

This paper proposes a methodology for high-level error propagation analysis of real-time data-intensive systems. A formal system in C-style programming language is proposed to provide a research framework for various issues on real-time system designs. A symbolic procedure is then presented to formally verify the amount of data errors tolerable to systems.

With the ever-increasing complexity of hardware (HW) and SoC-based designs for mobile platforms, demand for scalable formal verification tools in the semi-conductor industry is always growing. The scalability of hardware model checking tools depends on three key factors: the design representation, the verification engine, and the proof engine. Conventional SAT-based bit-level formal property ch...

This paper presents an approach towards real-time veriication of Statemate 1 designs. Statemate is a widely used design tool for embedded control units. These embedded control units are usually contained in industrial products and often implement concurrent systems. In our approach designs including all timing information are translated into untimed Kripke Structures which are optimized and the...

Formalhardware veriication based on symbolic trajectory evaluation shows considerable promise in verifying medium to large scale VLSI designs with a high degree of automation. However, in order to verify today's designs, a method for composing partial veriication results is needed. One way of accomplishing this is to use a general purpose theorem prover to combine the veri-cation results obtain...

This paper presents a toolset for real-time veriication of Statemate 1 designs. Statemate is a widely used design tool for embedded control applications. In our approach designs including all timing information are translated into untimed nite state machines (FSMs) which are veriied by symbolic model-checking. Real-time requirements are expressed by TCTL formulae interpreted over discrete time....

BACKGROUND The study aimed to compare trochlear profiles in recent total knee arthroplasty (TKA) models and to determine whether they feature improvements compared to their predecessors. The hypothesis was that recent TKA models have more anatomic trochlear compartments and would display no signs of trochlear dysplasia. METHODS The authors analyzed the geometry of the 6 following TKA models u...