We present a Built-In Self-Test (BIST) approach for programmable embedded memories in Xilinx Virtex-4 Field Programmable Gate Arrays (FPGAs). The target resources are the block random access memories (RAMs) in all of their modes of operation including singleand dual-port RAM, first-in first-out (FIFO), error correcting code (ECC), and cascade modes of operation. The BIST architecture and config...

The low power as a feature of a BIST scheme is a significant target due to quality as well as cost related issues. In this paper we examine the testability of multipliers based on Booth encoding and Wallace tree summation of the partial products and we present a methodology for deriving a low power Built In Self Test (BIST) scheme for them. We propose several design rules for designing the Wall...

This paper has emphasis on the novel sequence generation for the hardwired built in self test (BIST) of static random access memory (SRAM). It reduces the testing time of SRAM by generating all the pattern sequence in less time. BIST is a design technique that allows a circuit to test itself. Linear feedback shift register (LFSR) was used for the sequence generation in the BIST but novel sequen...

This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently combines several testing and test data compression approaches to enable application of a huge amount of ATPG and Weighed Random-BIST (WR-BIST) patterns. Results obtained from the application of the H-DFT technique to ...

This paper proposes a new DAC BIST (digital-to-analog converter built-in self-test) structure using a resistor loop known as a DDEM ADC (deterministic dynamic element matching analog-to-digital converter). Methods for both switch reduction and switch effect reduction are proposed for solving problems related to area overhead and accuracy of the conventional DAC BIST. The proposed BIST modifies ...

For system-on-chip designs that contain an embedded processor, this paper present a software based diagnosis scheme that can make use of the processor to aid in diagnosis in a scan-based built-in self-test (BIST) environment. The diagnosis scheme can be used to determine both the scan cells that capture errors as well as the failing test vectors during a BIST session thereby allowing a faster a...

A test-per-clock BIST method for combinational or full-scan circuits is proposed. The method is based on a design of a combinational block the decoder, transforming pseudo-random LFSR code words into deterministic test patterns. A Column-Matching algorithm to design the decoder is proposed. The Column-Matching method modified to support a mixed-mode BIST is proposed as well. Here the BIST is di...

In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson counter and is called folding counter. Both the theoretical background and practical algorithms are presented to characterize a set of deterministic test cubes by a reasonably small number of seeds for a folding counte...

This paper details our allocation for Built-in Self Test (BIST) technique used in the Interactive Design for Test reuse in Allocation for Testability (IDAT) tool. IDAT tool objective is to fullll the designer requirements regarding selected design and testability attributes of a circuit data-path to be synthesized. A related tool is used to synthesize a test controller for the nal testable circ...

Controlling or reducing power consumption during test and reducing test time are conflicting goals. Weighted random patterns (WRP) and transition density patterns (TDP) can be effectively deployed to reduce test length with higher fault coverage in scan-BIST circuits. New test pattern generators (TPG) are proposed to generate weighted random patterns and controlled transition density patterns t...