In this paper new multiplier and square architecture is proposed based on algorithm of ancient Indian Vedic Mathematics, for low power and high speed applications. It is based on generating all partial products and their sums in one step. The design implementation is described in both at gate level and high level RTL code (behavioural level) using Verilog Hardware Description Language. The desi...

High speed execution of arithmetic operations and high degree of precision in real time system are of major concern in any digital signal processing (DSP). Speed of DSP depends on speed of multiplier and algorithm used. In this paper we propose Residue Number System method for fast “carry free” floating point arithmetic operations. Floating Point RNS units have obvious advantages over tradition...

The capacity for semantic memory-the ability to acquire and store knowledge of the world-is highly developed in the human brain. In particular, semantic memory assimilated through an auditory route may be a uniquely human capacity. One method of obtaining neurobiological insight into memory mechanisms is through the study of experts. In this work, we study a group of Hindu Vedic priests, whose ...

The idea for designing the Divider unit is adopted from ancient Indian mathematics "Vedas" .Vedic Mathematics is the old method of computing. With the advent of new technology in the fields of VLSI and communication, there is also an always increasing demand for high speed processing and low area design. Divider is an important fundamental function in arithmetic operations. It is also known fac...