technology with through-silicon vias and low-volume leadfree interconnections K. Sakuma P. S. Andry C. K. Tsang S. L. Wright B. Dang C. S. Patel B. C. Webb J. Maria E. J. Sprogis S. K. Kang R. J. Polastre R. R. Horton J. U. Knickerbocker Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidt...

Several bis(hydrosulfido)-bridged dinuclear rhodium(I) compounds, [{Rh(mu-SH)(L)(2)}(2)], have been prepared from rhodium(I) acetylacetonato complexes, [Rh(acac)(L)(2)], and H(2)S(g). Reaction of [Rh(acac){P(OPh)(3)}(2)] with H(2)S(g) affords the dinuclear bis(hydrosulfido)-bridged compound [{Rh(mu-SH){P(OPh)(3)}(2)}(2)] (1). However, reaction of complexes [Rh(acac)(CO)(PR(3))] with H(2)S(g) gi...

Through-silicon via (TSV) technology enables 3D-integrated devices with higher performance and lower cost as compared to 2D-integrated systems. This is mainly due to smaller dimensions of the package and shorter internal signal lengths with lower capacitive, resistive and inductive parasitics. This paper presents a novel low-cost fabrication technique for metal-filled TSVs with very high aspect...

Pre-mRNA splicing is a fundamental process required for the expression of most metazoan genes. It is carried out by the spliceosome, which catalyzes the removal of noncoding intronic sequences to assemble exons into mature mRNAs prior to export and translation. Given the complexity of higher eukaryotic genes and the relatively low level of splice site conservation, the precision of the splicing...

The distribution of nucleotide sequences resembling functional sites for mRNA splicing was examined by computer-directed searches in order to determine what factors may influence splice site selection in nuclear precursors. In particular, the distribution of large potentially stable hairpin structures or regions of extensive dyad symmetry was studied in adenovirus sequences. One region, spannin...

The application of Cu-filled through-silicon via (TSV) in 3-D integrated circuit packaging faces several fabrication and reliability issues. In this study, we introduced a Cu-Ni alloy for TSV filling with a high filling speed and a reduced TSV protrusion. In particular, the characteristics of Cu-Ni via protrusions at various annealing temperatures (3200­450°C) were investigated with experimenta...

As compared to two-dimensional (2D) ICs, 3D integration is a breakthrough technology of growing importance that has the potential to offer significant performance and functional benefits. This emerging technology allows stacking multiple layers of dies and resolves the vertical connection issue by through-silicon vias (TSVs). However, though a TSV is considered a good solution for vertical conn...

1. Introduction As the size of transistor keeps shrinking, advance of CMOS technology becomes more difficult and will eventually reach the physical limitation. To continuously reduce the form factor of the system with multiple chips, one straight forward solution is using stacked dies, called three-dimensional integrated circuits (3D IC). Recently, the technology of Through Silicon Vias (TSVs),...

THE 2009 Design, Automation, and Test in Europe (DATE) conference, which took place in April in Nice, France, hosted a new workshop on 3D integration. The topic was vertical stacking of multiple silicon dies, interconnected by through-silicon vias, which is a promising technology. TSVs offer higher transistor density, faster interconnects, heterogeneous technology integration, and potentially l...

Now a day's one of the most crucial issues in the field of FPGAGs, especially in SRAM FPGAs is single event upsets. One of the most effective methods to decrease these errors is using three dimensional FPGAs. This paper presents evaluation and mitigation of SEU cost on six layers three-dimensional (3D) FPGAs. The evaluation results show that SUE rate decrease about 67% on six layers 3D FPGAs. W...