The compiler is generally regarded as the most important software component that supports a processor design to achieve success. This paper describes our application of the open research compiler infrastructure to a novel VLIW DSP (known as the PAC DSP core) and the specific design of code generation for its register file architecture. The PAC DSP utilizes port-restricted, distributed, and part...

As mobile applications are required to handle more computing-intensive tasks, many mobile devices are designed using VLIW processors for high performance. In VLIW machines where a single instruction contains multiple operations, the power consumption during instruction fetches varies signi cantly depending on how the operations are arranged within the instruction. In this paper, we describe a p...

This paper introduces the All-Pairs Common Slack Graph (APCSG), an intermediate representation of the instruction level parallelism that exists within a computation. The APCSG is intended for use in high level synthesis systems and compilers that target VLIW architectures. To exploit the benefits of the APCSG, we have developed the Parallel Template Generation Algorithm, a general purpose frame...

Clustering is an approach that many microprocessors are adopting in recent times in order to mitigate the increasing penalties of wire delays. In this work we propose a novel clustered VLIW architecture which has all its resources partitioned among clusters, including the cache memory. A modulo scheduling scheme for this architecture is also proposed. This algorithm takes into account both regi...

SAD (Sum of Absolute Difference) algorithm is heavily used in motion estimation which is computationally highly demanding process in motion picture encoding. To enhance the performance of motion picture encoding on a VLIW processor, an efficient implementation of SAD algorithm on the VLIW processor is essential. SAD algorithm is programmed as a nested loop with a conditional branch. In VLIW pro...

Very Long Instruction Word Architectures (VLIW architectures) can exploit the ne{grained (instruction level) parallelism typically found in sequential{natured program code. A parallelizing compiler is used to restructure the program code. Sophisticated global compaction techniques have emerged that can e ectively extract ne{grained parallelism from ordinary sequential natured program code. In t...

The high latency of memory operations is a problem in both sequential and parallel computing. Multithreading is a technique, which can be used to eliminate the delays caused by the high latency. This happens by letting a processor to execute other processes (threads) while one process is waiting for the completion of a memory operation. In this paper we investigate the implementation of multith...

Media processing has motivated strong changes in the focus and design of processors. These applications are composed of heterogeneous regions of code, some of them with high levels of DLP and other ones with only modest amounts of ILP. A common approach to deal with these applications are μSIMD-VLIW processors. However, the ILP regions fail to scale when we increase the width of the machine, wh...

Gene annotation is by nature a computationally intensive problem, as it needs to process huge data size of DNA sequences. This forces the need to look for alternate ways of implementing algorithms to predict exons. The paper presents a hardware-based approach in which a Digital Signal Processor is programmed to compute the computationally expensive part of the algorithm. The processor effective...