Recent advances in VLSI and fiber optic technology are shifting application performance bottlenecks from the underlying networks to the transport system and higher-layer communication protocols. Developing process architectures that effectively utilize multi-processing is one promising technique for alleviating these performance bottlenecks. This paper describes a flexible framework called ADAP...

To develop the semiconductor industry in any country, working knowledge of VLSI circuit design is crucial. galvanize undergraduate students to learn and work burgeoning field VLSI, a competition, “VLSI Design Competition 2022,” was jointly organized by IEEE Solid-State Circuits Society (SSCS)/Electron Devices (EDS) Bangladesh Joint Chapter Department Electrical Electronic Engineering (EEE), Uni...

In this paper, novel pipelined architectures for the implementation of the frequency domain linear equalizer are presented. The Frequency Domain (FD) LMS algorithm is utilized for the adaptation of equalizer coefficients. The pipelining of the FD LMS linear equalizer is achieved by introducing an amount of time delay into the original adaptive scheme, and following proper delay retiming. Simula...

A Montgomery’s algorithm in GF(2) based on the Hankel matrix–vector representation is proposed. The hardware architecture obtained from this algorithm indicates low-complexity bit-parallel systolic multipliers with irreducible trinomials. The results reveal that the proposed multiplier saves approximately 36% of space complexity as compared to an existing systolic Montgomery multiplier for trin...

Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative architectures are operated both for encryption and decryption process. They reduce the required hardware resources and achieve high-speed performance. Their design philosophy is completely different. The first uses feedback logic and reaches a throughput value equal to 259 Mb...

In this paper, a generalized Montgomery multiplication algorithm in GF(2m) using the Toeplitz matrix-vector representation is presented. The hardware architectures derived from this algorithm provide low-complexity bit-parallel systolic multipliers with trinomials and pentanomials. The results reveal that our proposed multipliers reduce the space complexity of approximately 15% compared with an...

A class of motion estimation VLSI architectures is presented which has been developed for the use in studio quality MPEG2 encoders. A new, fast motion estimation algorithm is applied which exploits both, temporal and spatial redundancies in motion vector fields and delivers near full search quality on large search windows. The proposed architectures are MIMD based, scalable both on chip and sys...

In this paper, a VLSI architecture for lifting-based shape-adaptive discrete wavelet transform (SA-DWT) with odd-symmetric filters is proposed. The proposed architecture is comprised of a stage-based boundary extension strategy and the shape-adaptive boundary handling units. The former could reduce the complexity of multiplexers that are introduced to solve the shape-adaptive boundary extension...

The design of electronic circuits can be achieved at many different refinement levels from the most detailed layout to the most abstract architectures. Given the complexity of Very Large Scaled Integrated Circuits (VLSI) which is far beyond human ability, computers are increasingly used to aid in the design and optimization processes. It is no longer efficient to use manual design techniques, i...

Abstract—In this paper a new very large scale integration (VLSI) algorithm for a 2N-length discrete Hartley transform (DHT) that can be efficiently implemented on a highly modular and parallel VLSI architecture having a regular structure is presented. The DHT algorithm can be efficiently split on several parallel parts that can be executed concurrently. In this we present a new approach to desi...