Wireless sensor networks are often located in areas where access to them is difficult or dangerous. Today, in wireless sensor networks, cluster-based routing protocols by dividing sensor nodes into distinct clusters and selecting local head-clusters to combine and send information of each cluster to the base station and balanced energy consumption by network nodes, get the best performance ...

To support high bandwidth SoCs, a communication design flow is necessary for the design space exploration respecting tight design requirements. In order to exploit the benefits introduced by the NoC approach for the on-chip communication, the paper presents a design flow for the core mapping and customization of the network topology applied to STNoC, the Network on-Chip developed by STMicroelec...

With the emergence of the packet-switched networks as a possible system-on-chip (SoC) communication paradigm, the design of network-on-chips (NoC) has provided a challenge to the designers. Meeting latency requirements of communication among various cores is one of the crucial objectives for system designers. The core interface to the networking logic and the communication network are the key c...

Congestion in on-chip networks may cause many drawbacks in multiprocessor systems including throughput reduction, increase in latency, and additional power consumption. Furthermore, conventional congestion control methods, employed for on-chip networks, cannot efficiently collect congestion information and distribute them over the on-chip network. In this paper, we present an on-chip network ar...

A conventional Network-on-Chip (NoC) router uses input buffers to store packets to improve performance, but consume significant power. While bufferless NoC design has shown reduction in area and power, and offers similar performance to conventional buffered designs for many workloads, than conventional buffered routers at high network load. This degradation is a significant problem for widespre...

This paper proposes a new methodology to design of coarse-grained routers in order to improve performance of Networks-on-Chip (NOC). In this approach, several cluster routers in region area of K×K are grouped into one new router called K2Router with similar cost of area and power, however, the performance of whole network is improved. The proposed routers are general in terms of constructions a...

The design of recent Systems-on-Chip (SoC) for a large scope of applications, such as telecom and multi-media domains, and in various platform types ranging from dedicated platforms to fully programmable platforms, is mainly constrained by communications. Networks-on-Chip (NoC) have recently emerged as a promising concept to support communication on SoCs providing a solution to connect differen...

Network-on-Chip (NoC) paradigm has been proposed as an alternative bus-based schemes to achieve high performance and scalability in System-on-Chip (SoC) design. Performance analysis and evaluation of on-chip interconnect architectures are widely considered. Time latency and throughput are two very critical parameters which play vital role to improve the system performance. In this work, these t...

simultaneous routing and resource allocation has been considered in wireless networks for its performance improvement. in this paper we propose a cross-layer optimization framework for worst-case queue length minimization in some type of fdma based wireless networks, in which the the data routing and the power allocation problem are jointly optimized with fuzzy distributed h∞ control strategy ....