Reconfigurable architectures offer potential for performance enhancement by specializing the implementation of floating-point arithmetic. This paper presents FloatWatch, a dynamic execution profiling tool designed to identify where an application can benefit from reduced precision or reduced range in floating-point computations. FloatWatch operates on x86 binaries, and generates a profile outpu...

Reconfigurable architectures offer potential for performance enhancement by specializing the implementation of floating-point arithmetic. This paper presents FloatWatch, a dynamic execution profiling tool designed to identify where an application can benefit from reduced precision or reduced range in floating-point computations. FloatWatch operates on x86 binaries, and generates a profile outpu...

The performance of the many-core Tile64 versus the multi-core Xeon x86 architecture on bioinformatics has been compared. We have used the pairwise algorithm MC64-NW/SW that we have previously developed to align nucleic acid (DNA and RNA) and peptide (protein) sequences for the benchmarking, being an enhanced and parallel implementation of the Needleman-Wunsch and Smith-Waterman algorithms. We h...

This paper describes our experience in today’s working of JVM which we use is platform dependent ,it create an issue regarding Java being platform independent .The different platform uses different JVM architecture like RISC and CISC use different JVM .This paper defines porting Compaq's Fast VM from the Alpha processor architecture to the Intel x86 processor architecture. We encountered severa...

Additive Cost Register Automata (ACRA) map strings to integers using a finite set of registers that are updated using assignments of the form “x := y + c” at every step. The corresponding class of additive regular functions has multiple equivalent characterizations, appealing closure properties, and decidable analysis questions. In this paper, we define the register complexity of an additive re...

Current multiprocessors provide weak or relaxed memory models. Existing program logics assume sequential consistency, and are therefore typically unsound for weak memory. We introduce a novel RelyGuarantee style proof system for reasoning about x86 assembly programs running against the weak x86-TSO memory model. Interesting features of the logic include processor assertions which can refer to t...

From a software developer’s perspective, fault injection (FI) is the most complete way of evaluating the sensitivity of a program against hardware errors. Unfortunately, FI campaigns require a substantial investment of both, time and computing resources, making their application infeasible in many cases. Program Vulnerability Factor (PVF) analysis has been proposed as an alternative for estimat...

ÐIn this paper, we examine the effectiveness of a new hardware mechanism, called Register Queues (RQs), which effectively decouples the architected register space from the physical registers. Using RQs, the compiler can allocate physical registers to store live values in the software pipelined loop while minimizing the pressure placed on architected registers. We show that decoupling the archit...

Power consumption in a set of registers is a function of switching activity at the inputs of these registers which is in turn affected by the sharing of registers among compatible data values. Data streams that are input to a circuit have probability distributions. Based on the assumption that the joint probability density function of the primary input variables is known or that a sufficiently ...

translation of an x86 BB to PPC DARCO main components