Bitwise operations are an important component of modern day programming. Many widely-used data structures (e.g., bitmap indices in databases) rely on fast bitwise operations on large bit vectors to achieve high performance. Unfortunately, in existing systems, regardless of the underlying architecture (e.g., CPU, GPU, FPGA), the throughput of such bulk bitwise operations is limited by the availa...

Zölfet Hekim, XX. yüzyılın sonu ve XXI. başı Tatar Edebiyatının önde gelen isimlerinden birisidir. Makalede Hekim’in Edebiyatındaki yeri, eserleri, edebî kişiliği, eserlerinde kullandığı üslup bakış açısı üzerinde durulmuştur. Yazar, şair, dram ustası ses sanatçısı olan Zölfet, hayatı insanları gözlemleyerek kimi zaman komik hicivli da gerçekçi bir biçimde duygularını düşüncelerini sanata yansı...

Class Based Queueing (CBQ) is a link-sharing and resource management mechanism for packet networks. The weights of CBQ control the way with which the available bandwidth at the output interface of the router is distributed among the different classes of the input traffic. CBQ also disposes of rules for bandwidth borrowing based on a hierarchy of classes. In [1], we proposed a dynamic, self-tuni...

Abstract The MICRO 2011 paper “Efficiently Enabling Conventional Block Sizes for Very Large Die-stacked DRAM Caches” proposed a novel die-stacked DRAM cache organization embedding the tags and data within the same physical DRAM row and then using compound access scheduling to manage the hit latency and a MissMap structure to make misses more efficient. This addendum provides a revised performan...

Dramatic increase in the number of transistors that can be integrated on a chip, coupled with advances in Merged Logic DRAM (MLD) technology fuels the interest in Processor In Memory (PIM) architectures. A promising use of these architectures is as the intelligent memory system of a workstation or server. In such a system, each memory chip includes many simple processors, each of which is assoc...

In this paper, we present an extension of the NVMain memory simulator. The objective is to facilitate computer architects to model complex memory designs for future computing systems in an accurate simulation framework. The simulator supports commodity memory models for DRAM as well as emerging non-volatile memories technologies such STT-RAM, ReRAM, PCRAM and hybrid models. The current publicly...

Bum-Sik Kim, Yun Ho Choi , and Lee-Sup Kim Korea Advance Institute of Science and Technology E-mail:[email protected] *SAMSUNG Electronics Co., LTD. E-mail:[email protected] Abstract There are strong demands for high speed and low power to realize systems on silicon. However, the current circuit design technologies for MPU and DRAM are based on their own optimized process technolog...

BACKGROUND Drug-resistance mutations (DRAM) are frequently selected in patients with virological failure defined as viral load (pVL) above 500 copies/ml (c/mL), but few resistance data are available at low-level viremia (LLV). Our objective was to determine the emergence and evolution of DRAM during LLV in HIV-1-infected patients while receiving antiretroviral therapy (ART). METHODS Retrospec...

The disk and the DRAM in a typical mobile system consume a significant fraction (up to 30%) of the total system energy. To save on storage energy, the DRAM should be small and the disk should be spun down for long periods of time. We show that this can be achieved for predominantly streaming workloads by connecting the disk to the DRAM via a large non-volatile memory (NVM). We refer to this as ...