Time interleaved sigma-delta (TIΣΔ) architecture is a potential candidate for high bandwidth analog to digital converters (ADC) which remains a bottleneck for software and cognitive radio receivers. However, the performance of the TIΣΔ architecture is limited by the unavoidable gain and offset mismatches resulting from the manufacturing process. This paper presents a novel digital calibration m...

There has recently been increasing interest in developing highly digital analog-to-digital converter (ADC) structures for on-chip testing and ease of integration in future CMOS processes. An intriguing circuit to utilize in such cases is a ring oscillator voltage-controlled oscillator (VCO), which outputs a clock waveform whose frequency is a function of an input tuning voltage. By comparing th...

Based on a conventional flash architecture a 4-bit GaAs analog to digital (A/D) converter has been designed using OMMIC-Philips GaAs foundry and particularly its commercial enhancement/depletion mode 0.18 μm pHEMT technology process. The ADC operates at 7.5 GHz sampling rate with full power analog input bandwidth from DC to Nyquist frequency. Differential source coupled FET logic (SCFL) was use...

i ABSTRACT A dual-channel directional digital hearing aid (DHA) front end using Micro Electro Mechanical System (MEMS) microphones and an adaptive-power analog processing signal chain is presented. The analog front end consists of a double differential amplifier (DDA) based capacitance to voltage conversion circuit, 40dB variable gain amplifier (VGA) and a continuous time sigma delta analog to ...

The wireless market is developing very fast today with a steadily increasing number of users all around the world. An increasing number of users and the constant need for higher and higher data rates have led to an increasing number of emerging wireless communication standards. As a result there is a huge demand for flexible and low-cost radio architectures for portable applications. Moving tow...

Abstract During the last decades we have witnessed performance improvement and aggressive growth of complexity integrated circuits (ICs). The progressive size reduction transistors in recent technological nodes has allowed even compelled IC designers to perform analog tasks digital domain, increasing demand for analog-to-digital converters (ADCs). This work presents design implementation a low ...

A low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed. The proposed SAR ADC nonbinary-weighted multiple-LSB-redundant CDACs has an optimal mechanism for correcting the bit error decisions due to noise incom...

This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with single open-loop residue amplifier (RA). By using the inherent characteristics of SAR conversion scheme, proposed ADC sequentially generates two levels from RA, which eliminates need for inter-stage gain-matching calibration. To convert generated residues, ...

With the ever-growing demands for sampling rate, conversion resolution, as well lower energy consumption, memristor-based neuromorphic analog-to-digital converters (MN-ADC) becomes one of most potential approaches to break bottleneck traditional ADCs. However, online trainable MN-ADCs are not designed be easily integrated into 1T1R crossbar array, meanwhile suffering from device non-idealities,...

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its...