This paper presents a hardware implementation of a fully synthesizable, technology-independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter. Frequency control is done by using a robust regulation algorithm to allow a defined lock-in time of at most eight referenc...

This paper summarizes the objectives and some early results of the ESPRIT project 29260 BANDIT. It is a 3 year project that started in September 1998. Coordinating partner is IMEC and the other partners are K.U.Leuven and Ericsson Radio Systems (ERA). The goal of BANDIT is to develop a general design and test methodology for embedding high-speed analog/digital converters (ADCs) on large digital...

Hardware resources can be shared to reduce the area of the resulting design. The synthesis system must ensure that no resource conflicts arise due to simultaneous access of a shared hardware resource. With traditional scheduling formulations where operations are statically assigned to control steps, conflict resolution simply determines whether two operations can execute concurrently based on t...

A mixed-signal IC controller is described for singlephase PFC applications. The single-chip controller block diagram is described, and the fundamental analog and digital operating blocks are developed in detail. Implementation options for each block are given, with experimental results from a 1.2μ CMOS test chip included. The controller blocks are derived for boost and buck/boost type converter...

Logic synthesis is the process of automatically generating optimized logic level representation from a high-level description. With the rapid advances in integrated circuit technology and the resultant growth in design complexity, designers increasingly rely on logic synthesis to shorten the design time, while achieving performance objectives. This paper describes the IBM logic synthesis system...

This paper concerns the design and development of an Application Specific Integrated Circuit (ASIC) for the implementation of the Transmission Convergence sub-layer of the xDSL protocols. The work presents the required functionalities and focalizes on the hardware and software architecture of the module. Key-Words: ADSL, VDSL, G.Lite, xDSL, ATM, Transmission Convergence sub-layer, ASIC

Deep packet processing is migrating to the edges of service provider networks to simplify and speed up core functions. On the other hand, the cores of such networks are migrating to the switching of high-speed traffic aggregates. As a result, more services will have to be performed at the edges, on behalf of both the core and the end users. Associated network equipment will therefore require hi...

The Compact Muon Solenoid (CMS) calorimeter regional trigger system is designed to detect signatures of isolated and nonisolated electrons/photons, jets, τ-leptons, and missing and total transverse energy using a deadtimeless pipelined architecture. This system contains 18 crates of custom-built electronics. The pre-production prototype backplane, boards, links and Application-Specific Integrat...

Since the semiconductor industry hit the 0.18-micron generation, device feature sizes have become increasingly smaller than the wavelength of light used by available optical-lithography equipment. In this subwavelength arena, manufacturing requirements must be handled up front in the IC design stage—while changes can still be made—to enhance quality and yield. This paper defines the components ...

The reverse converter is the most complex and essential part of residue number system (RNS), and has a significant role in the general performance of RNS. Recently, it is showed that the reverse converter performance could be significantly improved using different adder’s type in the architecture of reverse converters, rather than just using one type of adder topology. This technical report aim...