Development of a single chip packaged MEMS G sensor for industrial applications is discussed. The developed G sensor is composed of a MEMS sensing element and a signal processing ASIC. The MEMS sensing element is fabricated by using the unique sacrificial/bulk micromachining (SBM) process for better mechanical properties. And the signal processing ASIC is fabricated in 0.5um CMOS process techno...

In this paper we present the implementation results for all five SHA-3 third round candidate algorithms, BLAKE, Grøstl, JH, Keccak, and Skein in a standard-cell-based ASIC realized using 65nm CMOS technology. The ASIC includes two sets of implementations developed independently and with different optimization targets, and includes a reference SHA-2 implementation as well. We believe that having...

The paper presents an ASIC to be used in one of the instruments of Rosetta Lander – a spacecraft that will investigate properties of comet 46 P/Wirtanen nucleus. The Rosettabis chip integrates a number of analog and digital modules of densitometer and thermal conductivity measurement subsystems. In addition to chip architecture and design methodology some problems typical for space application ...

encountered in ASIC (applicationspecific integrated circuit) developments originate from unclear or incorrectly implemented specifications. To allow independent evaluation of a device’s functionality, the European Space Agency (ESA) normally requests a VHDL model before a company starts the detailed design. This allows ESA or another company to verify the functionality. (For more about ESA and ...

While serial transceivers move data in and out of an ASIC, on-chip global interconnects move data inside the ASIC. These global interconnects include crossbar switches and busses for sharing on-chip resources. To guarantee quality of service, the on-chip global interconnects are often designed to carry several times worth of traffic compared to the serial transceivers. Close to 10 Tb/s is not a...

This work presents the architecture and ASIC implementation of Hermes-A, an asynchronous network on chip router. Hermes-A is coupled to a network interface that enables communication between router and synchronous processing elements. The ASIC implementation of the router employed standard CAD tools and a specific library of components. Area and timing characteristics for 180nm technology attes...

This paper proposes a modified predictive direct torque control (PDTC) application-specific integrated circuit (ASIC) of a motor drive with a fuzzy controller for eliminating sampling and calculating delay times in hysteresis controllers. These delay times degrade the control quality and increase both torque and flux ripples in a motor drive. The proposed fuzzy PDTC ASIC calculates the stator’s...

There are a number of physical failure mechanisms that can affect the reliability of a CMOS ASIC. Some of the common mechanisms can be mitigated by adhering to foundry design rules (Electromigration, Time Dependent Dielectric Breakdown (TDDB), and Hot Carrier Damage). Certain fabrication steps can cause stress that may lead to latent damage that may later reduce the useful lifetime of an ASIC. ...

INTRODUCTION THE demand for higher functionality and technical complexity, and the implementation of smaller device size and lower power dissipation, present demanding technological challenges that need to be resolved for the emerging multimedia and portable markets. Today, a major problem is how to deal with time-to-market cycles (sales cycles) due to shorter product lifetimes and shorter desi...