Timed asynchronous circuits can be implemented using commercial computer-aided design (CAD) tools. Relative timing methodology is applied for interpreting the complex timing of asynchronous circuits into CAD tools that can be understood with minimum and maximum timing constraints. Typical synchronous placement algorithm neglect timing information which is critical for asynchronous methodology. ...

Computing and Communications are well understood topics in engineering. However, we are very much at the beginning of the road to understanding those mechanisms in biological systems. I'll argue that progress in Biology will require better understanding of biologically inspired paradigms for computing and communications. In particular, I'll discuss some initial results related to asynchronous c...

Asynchronous text-based communication has long been established as having value in supporting the collaborative sharing of knowledge. However, in cases where learners or practitioners are seeking to acquire skills applicable in real-world working contexts, this kind of technology proves to be insufficient. Asynchronous multimedia conferencing seems both suitable and sufficient for supporting su...

This paper surveys the most promising low-power and energy-efficient asynchronous design techniques that can lead to substantial advantages over synchronous counterparts. Our discussions cover macro-architectural, micro-architectural, and circuit-level differences between asynchronous and synchronous implementations in a wide range of designs, applications, and domains including microprocessors...

This paper discusses the integration of model-checking inside a design flow for Quasi-Delay Insensitive circuits. Both the formal validation of an asynchronous behavioral specification and the formal verification of the asynchronous synthesis result are considered. The method follows several steps: formal model extraction, model simplification, environment modeling, writing temporal properties ...

An asynchronous unit delay is an n input n output of the input n-tuple prior to the last inlput change. It asynchronous sequential circuit in which the present value of the will then be shown that every asynchronous definite flow output n-tuple is equal to the value of the input n-tuple prior to the last input change. This paper considers the problem of determining ablecan brizeday a fee bac r ...

A testing method and on-chip testing circuits for our VLSI chip of asynchronous communication mechanism (ACM) using self-timed circuits are presented in this paper. The three properties of ACMs, asynchrony, coherence and freshness, are what we want to test. Besides these, the general function of the chip and data loss are also of interest. Although this work is a specific solution for a specifi...

Adiabatic logic can offer significant power reductions in comparison to conventional CMOS circuits ([1], [2]). Although numerous architectures have been proposed in the literature for synchronous circuit implementations, not much work has been done on asynchronous logic due to the difficulties of such implementations. This paper presents a new adiabatic power supply controller for asynchronous ...

Traditionally, circuits with combinational loops are found only in asynchronous designs. However, combinational loops can also be useful for synchronous circuit design. Combinational loops can arise from high-level language behavioral compiling, and can be used to reduce circuit size. We provide a symbolic algorithm that detects if a sequential circuit with combinational loops exhibits standard...