Asynchronous design methodologies can yield designs that are smaller, and/or consume less power, than their synchronous counterparts. Traditional tools, oriented toward synchronous designs, may miss critical asynchronous design problems. This paper describes the modeling methodology and hazard analysis of the SIMIC logic simulator that address asynchronous designs. It also describes XPOWER, an ...

This paper is concerned with the problem of reMizing a sequential machine M by a sequential circuit with a single feedback loop carrying a binary signal. To find such a realization, one must find a binary total-state partit ion, which can be used for feedback, for the flow table T of M or for some expanded version of T. A method is presented for testing whether a given flow table possesses a fe...

A steering fragment of an instruction sequence consists of a sequence of steering instructions. These are decision points involving the check of a propositional statement in sequential logic. The question is addressed why composed propositional statements occur in steering fragments given the fact that a straightforward transformation allows their elimination. A survey is provided of constraint...

1 This paper presents a method of using hardware redundancy to ease the problem of fault testing in sequential logic networks. Sequential logic networks are constructed using two kinds of dual-mode logic gates, one of which is specifically required to initialize a feedback loop to some logic value. Initially, it is shown that these networks can be tested for all single stuck-at-faults with six ...

In order to determine the applicability of both programmable software tools and pro-grammable hardware for asynchronous logic applications an implementation, employing FPGA devices, of the instruction decode and the instruction execution stages of an asyn-chronous microprocessor, the ADLX, is presented. The foundation for that microprocessor is based on the employment of event driven logic, spe...

Globally Asynchronous Locally Synchronous (GALS) systems are popular both in software and hardware for specifying and producing embedded systems as well as electronic circuits. In this paper, we propose a method for obtaining automatically a GALS system from a centralised synchronous circuit. We focus on an algorithm that takes as input a program whose control structure is a synchronous sequent...

Introduction Asynchronous logic is enjoying a resurgence of interest and is poised to resume a role in commercial electronics which it has not played for a few decades, despite its use in some of the earliest computers. For the last twenty years electronic design has been dominated by the use of clocks to control communication and state transitions. The clock, like the conductor of an orchestra...

This project presents a high-throughput and ultralowpower asynchronous domino logic pipeline design method, targeting to latch-free and extremely fine-grain or gate-level design. The data paths are composed of a mixture of dual-rail and single-rail domino gates. Dual-rail domino gates are limited to construct a stable critical data path. Based on this critical data path, the handshake circuits ...