This paper proposes novel algorithms for computing test patterns for transition faults in combinational circuits and fully scanned sequential circuits. The algorithms are based on the principle that s@ vectors can be effectively used to construct good quality transition test sets. Several algorithms are discussed. Experimental results obtained using the new algorithms show that there is a 20% r...

We introduce SImulation Veriication with Augmentation (SIVA), a tool for checking safety properties on digital hardware designs. SIVA integrates simulation with symbolic techniques for vector generation. Speciically, the core algorithm uses a combination of ATPG and BDDs to generate input vectors which cover behavior not excited by simulation. Experimental results demonstrate considerable impro...

In this paper, an immune genetic based algorithm (IGA) for random test pattern generation was proposed. Genetic algorithms (GA) solve many search and optimization problems, effectively. However, they may drop into local optimal solutions; or they may find the optimal solution by low convergence speed. To overcome these problems, we used the immune concept and GA algorithm for random-based test ...

This work proposes a TPG method for producing maximal crosstalk glitch effect on victim net. Thereafter, the test set is compacted using different implementations of fault-list chaining algorithm.

Measuring the steady state leakage current (IDDQ) is a very successful testing paradigm detecting faults not discovered when considering standard fault models. Due to increasing vector dependencies and process variations IDDQ testing becomes more difficult. We propose ATPG algorithms to control test vector dependencies even before performing the IDDQ test. Experimental results show that leakage...

This paper investigates a method of using equivalent fault metrics to optimize N-detect scan ATPG patterns. The introduction goes over the motivation for using N-detect scan patterns and why dynamic N-detect patterns are useful. The next section discusses what equivalent fault metrics are and why equivalent fault metrics might apply to dynamic Ndetect scan patterns selection. We then present ex...

Recently, assertion based verification or property checking has become of great interest to the industry. Property checkers attempt either to prove that a specified property, which stipulates expected design behavior, holds or, if the property does not hold, to generate a counter-example that demonstrates a violation of the property. This is another area where there have been some promising suc...