Multiplication is the main finite field arithmetic operation in elliptic curve cryptography and its bit-serial hardware implementation is attractive in resource constrained environments such as smart cards, where the chip area is limited. In this paper, a new serial-output bitserial multiplier using polynomial bases over binary extension fields is proposed. It generates a bit of the multiplicat...

We introduce a new implementation of a three-input multiplier. This multiplier is capable of accepting three binary inputs, and producing the product, a*b*c. Although this implementation requires more space, it reduces the number of clock cycles required to multiply three numbers. In this paper, we present the front end 4-bit partial product array that can be incorporated into a typical multipl...

We present results on time borrowing in skew-tolerant domino logic circuits for a 32-bit adder, a 64-bit adder and a 32-bit pipelined multiplier. The adders are built using enhanced multiple output domino logic and the multiplier uses modified Booth encoding and a Wallace tree. We illustrate how the resulting soft clock edges allow advantageous time borrowing to occur in these functional units....

Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing technology is an advanced transmission technique for wireless communication systems. In this paper, the 64 point pipeline FFT/IFFT processor is introduced for efficient implementation of OFDM architecture. The IFFT processor is used to modulate the subcarrier in transmitter section and FFT processor demodulate the subcarr...

Bit-serial architectures have the advantage of high throughput, area efficient multipliers. These multipliers are implemented using shift-add operations [1], with full adders and D flip-flops as building blocks. Multiplication with a constant fixed-point coefficient is commonly used in digital signal processing (DSP) circuits, such as digital filters [2][3]. The design of a constant-coefficient...

In this paper we present the design of a new high-speed multiplication unit. The design is based on non-overlapped scanning of 3-bit ® elds of the multiplier. In this technique the partial products of the multiplicand and three bits of the multiplier are pre-calculated using only hardwired shifts. These partial products are then added using a tree of carry-save-adders, and ® nally the sum and c...

In this paper VHDL implementation of complex number multiplier using ancient Vedic mathematics and conventional modified Booth algorithm is presented and compared. The idea for designing the multiplier unit is adopted from ancient Indian mathematics "Vedas". The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. Multiplicatio...

In this paper a new bit-parallel structure for a multiplier with low complexity in Galois elds is introduced. The multiplier operates over composite elds GF((2 n) m), with k = nm. The Karatsuba-Ofman algorithm is investigated and applied to the multiplication of polynomials over GF(2 n). It is shown that this operation has a complexity of order O(k log 2 3) under certain constraints regarding k...

Montgomery multiplication in GF(2) is defined by a(x)b(x) r−1(x) mod f(x), where the field is generated by irreducible polynomial f(x), a(x) and b(x) are two field elements in GF(2), and r(x) is a fixed field element in GF(2). In this paper, first we present a generalized Montgomery multiplication algorithm in GF(2). Then by choosing r(x) according to f(x), we show that efficient architecture f...

In this paper we present a VHDL code generator for a complex multiplier. The complex multiplier is based on a bit-parallel version of distributed arithmetic which reduces the hardware by nearly half compared to a straightforward implementation based on real multipliers. We choose an Overturned-Stairs adder tree to perform the summations in distributed arithmetic. The tree has a regular structur...