A deterministic-partitioning technique and an improved analysis scheme for fault diagnosis in Scan-Based BIST is proposed. The incorporation of the superposition principle to the analysis phase of the diagnosis algorithm improves diagnosis times significantly; furthermore, the deterministic partitioning approach results in even further reductions in diagnosis times together with higher predicta...

Self-repairing system is alternative for fault tolerant systems. They lose efficiency when the circuit size increases, due to the extra hardware. In existing system, they used four spare cells for one working cell for cell replacement.In proposed system, there is no need to use spare cells permanently.In proposed system, we have taken RISC processor as a working cell for our consideration. BIST...

We propose several improvements to a previously proposed scheme of built-in test pattern generation for synchronous sequential circuits. The basic scheme consists of a parametrized structure for test pattern generation, where parameter values are determined randomly. The proposed improvements consist of an improved structure for test pattern generation that allows more flexibility in the determ...

In this letter a histogram-based BIST (Built-In Self-Test) approach for deriving the main characteristic parameters of an ADC (Analog to Digital Converter) such as offset, gain and non-linearities is proposed. The BIST uses a ramp signal as an input signal and two counters as a response analyzer to calculate the derived static parameters. Experimental results show that the proposed method reduc...

The paper presents a new approach to transparent BIST for wordoriented RAMs which is based on the transformation of March transparent test algorithms to the symmetric versions. This approach allows to skip the signature prediction phase inherent to conventional transparent memory testing and therefore to significantly reduce test time. The hardware overhead and fault coverage of the new BIST sc...

The paper describes a new system that automatically calibrates the linearity of a resistance thermometry bridge or readout. A thermometry bridge, like all measuring and test equipment, must be regularly tested to ensure it is operating properly and accurately. Previously, this could only be done using special equipment and time-consuming procedures. The new technique described in the paper faci...

The trend of cramming more functionality onto a single chip poses alarming problems for testing and diagnosis. Complex chips such as those systems-on-silicon designs usually contain both digital and analog circuitry and include various cores from specialized design houses. Built-In Self-Test is an integrated test solution that could possibly hold down the soaring cost of external ATE machines f...

At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-test. However, due to their reliance on random patterns, current logic BIST techniques is not able to deal with large designs without adding high test overhead. In this paper, we propose a functional self-test technique...

High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution. By proving the effectiveness ...

This paper presents a segment weighted random built-in self test (SWR-BIST) technique for low power testing. This technique divides the scan chain into segments of different weights. Heavily weighted segments have more biased probability than lightly weighted segments. Heavily weighted segments are placed closer to the end of scan chain than the lightly weighted segments so the scan-in transiti...