Energy recovery clocking has been demonstrated as an effective method for reducing the clock power. However, in this method the conventional square wave clock signal is replaced by a sinusoidal clock generated by a resonant circuit. Such a modification in clock signal prevents application of existing clock gating solutions. In this paper, we propose clock gating solutions for energy recovery cl...

Clock recovery circuits are used in data communication systems for the system synchronization. In general a PLL (Phase Locked Loop) circuit is used to extract the clock signal from the input data stream. The recovered clock signal is always jittered and have to be adjusted by using a dejitter circuit. Tracking these errors over an extended period of time determines the system stability. Sources...

We have previously described a design for a 4Gb/s signaling system that uses transmitter equalization to overcome the frequency-dependent attenuation due to skin effect in transmission lines. We present here experimental results from an implementation of this idea in 0.5μ CMOS, showing the effectiveness of a simple transition-filter equalization technique. Our experimental chips use a tracking ...

Hypermethylation of the promoters of cancer-related genes is often associated with their inactivation during tumorigenesis. Several preclinical and clinical trials have been developed to use DNA methylation inhibitors, such as 5-aza-2'-deoxycytidine (5-Aza-CdR) in attempts to reactivate silenced genes in human cancers. We used high-density oligonucleotide gene expression microarrays to examine ...

In this paper an analysis on the oversampling data recovery circuit is presented. The input waveform is assumed to be non-return-zero (NRZ) binary signals. A finite Markov chain model is used to evaluate the steady-state phase jitter performance. Theoretical analysis enables us to predict the input signal-to-noise ratio (SNR) versus bit error rate (BER) of the oversampling data recovery circuit...