We propose conditional execution technique to reduce the redundant switching activity of the internal nodes in flip-flops. Double-edge clocking is utilized to further reduce the power consumption. With a data switching activity of 37.5%, the new conditional execution pulsed Flip-Flop (CEPFF) can achieve 12% improvement in terms of PDP.

This paper introduces one of the high speed CMOS clocking design style --time borrowing and time stealing. It starts with an introduction of traditional domino pipeline structure and its limits. In the following parts, time borrowing and time stealing and their usages are introduced respectively.

In this paper we consider the problem of determining a valid clock setting for a combinational circuit. The performance of a circuit depends on its clock period. The shorter a valid clock period is, the better the performance is. We rst consider the cases in which the primary input and output latches are triggered by the same clock signal but diierent phases. We have proposed two new bounds for...

In this issue, Willenbrock et al. (1) address how leukocytes achieve deceleration during rolling and arrest on endothelium in the vasculature near tissue sites of inflammatory insult. While cell capture from the blood stream and rolling is largely the functional domain of selectin adhesion receptors that are constitutively expressed on leukocytes and rapidly deployed on endothelium to bind glyc...

Recent advances of superconducting single-flux-quantum (SFQ) circuit technology make it attractive to investigate computing systems using SFQ circuits, where arithmetic circuits play important roles. In order to develop excellent SFQ arithmetic circuits, we have to design or select their underlying algorithms, called hardware algorithms, from different point of view than CMOS circuits, because ...

Adiabatic quantum-flux-parametron (AQFP) logic is an ultra-low-power superconductor family. AQFP gates are powered and clocked by dedicated clocking schemes using ac excitation currents to implement energy-efficient switching process, adiabatic switching. We have proposed a low-latency scheme, delay-line clocking, demonstrated basic gates. In order test more complex circuits, serializer/deseria...

Incentives, such as the Feed-in-tariff are expected to lead to continuous increase in the deployment of Small Scale Embedded Generation (SSEG) in the distribution network. Self-Excited Induction Generators (SEIG) represent a significant segment of potential SSEG. The quality of SEIG output voltage magnitude and frequency is investigated in this paper to support the SEIG operation for different ...