The binary adder is the critical element in most digital circuit designs including digital signal processors (DSP) and microprocessor data path units. As such, extensive research continues to be focused on improving the power delay performance of the adder. This paper proposes a new method for implementing a low power full adder by means of a set of Gate Diffusion Input (GDI) cell based multipl...

A parallel algorithm for finding Ramsey numbers is presented where analog/digital CMOS circuits for the hysteresis McCulloch-Pitts binary neuron are described. The hysteresis McCulloch-Pitts binary neuron model is used in order to suppress the oscillatory behaviors of neural dynamics so that the convergence time is shortened. The proposed algorithm using the hysteresis McCultoch-Pitts binary ne...

A fully integrated digitally controlled PLL used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. It is therefore portable between processes as an IP-block. Using a 0.35 μm standard CMOS process and a 3.0 V supply, the PLL has a frequency range of 152 MHz to 366 MHz and...

A digital readout electronics scheme in CMOS technology is described for integration with micro-electro-mechanical (MEM) sensors on the same chip. The readout circuit is general in nature and can be employed with a variety of analog sensors. The presented scheme in CMOS technology is fully integrable with the multiple sensor outputs either in a chain or an array format and is capable of detecti...

This paper presents a circuit including a high-pass Σ∆ modulator implemented in CMOS process and a timeinterleaved high-pass Σ∆ analog to digital converter.

The evolution of CMOS technology demands new approaches to implement radio-frequency integrated circuits. This paper presents two digital-intensive frequency synthesizers implemented in 65-nm CMOS: a digital period frequency synthesizer and an all-digital phase-locked loop. The experimental circuits cover frequency ranges of 0.1 4.3 GHz and 2.7 6.1 GHz.

A CMOS four-quadrant analog multiplier circuit for neural networks integrated circuit implementation is presented. By applying differential balanced current mode signals (both for the input, output and weight signals) the multiplication function is easily implemented through two translinear loops. The multiplier exhibits low power consumption (the dc current is 250 nA under a differential power...

We present a design of broadband and wide dynamic range low noise amplifier/radio frequency variable gain amplifier (LNA/RF VGA) for digital video broadcasting – satellite (DVBS2) receiver tuner integrated circuit fabricated using the 0.18 μm complementary metal oxide semiconductor (CMOS) process. The MOS switching filter was used to get broadband characteristics of the LNA circuit and the MOS ...

This paper presents a sample-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch. The heart of this circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced resulting in improved sample-and-hold accuracy. Simulation results ...

A CMOS image sensor with an integrated wire grid polarizer to sense the polarization of light is presented. The chip consists of an array of 128 by 128 pixels, and it has been designed and fabricated in a CMOS 180nm process. The sensed polarization information is represented and analyzed in both the analog and the digital domain. Extinction ratios of 6.3 and 7.7 were achieved in analog represen...