We present a dynamic and differential CMOS logic style, which has a signal independent switching behavior. It is shown that during each clock cycle, power consumption and all circuit characteristics, such as leakage current, instantaneous current and input-output delay are identical and independent of the logic value and the sequence of the input data. Implementing the encryption module in this...

In this paper, we present a noise-tolerant high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits in comparison with Domino logic have better scalability and they are more suitable for low voltage applications because of better noise margins. Skewed logic and its variations have been compared with Domino logic in terms of delay, powe...

Two new techniques for mapping circuits are proposed in this paper. The rst method, called the odd-level transistor replacement (OTR) method, has a goal that is similar to that of technology mapping, but without the restriction of a xed library size, and maps a circuit to a virtual library of complex static CMOS gates. The second technique, the Static CMOS/PTL method, uses a mix of static CMOS ...

We present the logic analysis, circuit implementation and verification of a novel selftimed adder scheme based on Carry Select (CS) logic. The preliminary analysis of the variabletime behavior of CS logic justifies the design of self-timed CS adders, and identifies the best choice for the block size to optimize the average performance. Hence we describe the logic design and full-custom circuit ...

Quantum-dot cellular automata (QCA) provide a novel electronics paradigm for information processing and communication. A basic quantum-dot cell consists of several quantum dots with two excess electrons. A binary coded decimal (BCD) and a decimal coded binary (DCB) circuit based on QCA logic gates: the and-or-inverter (AOI) gates are proposed in the study. In addition, the circuits designed by ...

Two architectures for a 1-V, 10-bit 200-kS/s successive approximation analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 μm digital process are presented. A track-andhold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch with a novel rail-to-rail trackand-latch comparator circuit is described. A pMOS-only ladder containing a rail-to-ra...

Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic...

Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. The increasing demand for low-power design can be addressed at different design levels, such as software, architectural, algorithmic, circuit, and process technology level. This paper presents different approaches to reduce power consumption of any arbitrary combinational logic circuit...

This paper presents a design strategy of eliminating signal degradation for memristor ratioed logic (MRL) gates. Based on the strategy, a novel MRL-based one-bit full adder is proposed. The inverters in circuit can effectively eliminate the degradation and restore signal integrity. To evaluate the effectiveness of the proposed one-bit full adder, an eight-bit full adder is demonstrated as a stu...

We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing short-circuit current by a piece-wise linear function and considering a current flowing from input node to output node through gate capacitances, the accuracy is improved significantly. The error of our formula in a CMOS inverter is less than 15% from circuit simulation in most cases of our expe...