In this paper I will describe how the efficiency of the Hangul writing system can be transferred to its coding on computers. I will also review the encodings of Hangul by the precomposed Hangul code set of KSC 5601, a combinational Hangul code set, and ISO 2022, and their applications to the development of Hangul pro grams for sorting, editing, and processing Korean text. I then conclude with r...

This paper describes a tunable transient filter (TTF) design for soft error rate reduction in combinational logic circuits. TTFs can be inserted into combinational circuits to suppress propagated single-event transients (SETs) before they can be captured in latches or flip-flops. TTFs are tuned by adjusting the maximum width of the propagated SET that can be suppressed. A TTF requires 6–14 tran...

This paper discusses a systematic methodology for calculating the aliasing probability when an arbitrary finite-state machine is used to compact the response of a combinational circuit to a sequence of randomly generated test input vectors. The proposed approach is general and is based on simultaneously tracking the states of two (fictitious) compactors, one driven by the response of the fault-...

Y. P. Chen and D. F. Wong Department of Computer Sciences The University of Texas at Austin Austin, Texas 78712 Abstract In this paper, we consider the problem of minimizing the number of logic modules for Actel 2 or Actel 3 sequential circuits. We make use of the fact that if a ipop is the only destination of its driving combinational block, then both the ipop and the combinational block can b...

We propose a procedure for determining fault detection tests for single and multiple fault in combinational circuits. The stuck-at-fault model is used. By the proposed procedure all test vectors for single and multiple stuck-at-fault in combinational circuit are determined. The path sensitization method is used in the test signal propagation while test signals are defined on a four element set....

The design automation of complex digital circuits offers important benefits. It allows the designer to reduce design time and errors, to explore more thoroughly the design space, and to cope effectively with an ever-increasing project complexity. This dissertation presents new algorithms for the logic optimization of combinational and synchronous digital circuits. These algorithms rely on a com...

This paper presents a comparison between the electroencephalogram (EEG) channels during scoliosis correction surgeries. Surgeons use many hand tools and electronic devices that directly affect the EEG channels. These noises do not affect the EEG channels uniformly. This research provides a complete system to find the least affected channel by the noise. The presented system consists of five sta...

Combinational equivalence checking is one of the key components in today’s hardware verification methodology. Structural similarity of the two designs are exploited by existing BDD, SAT, or ATPG based methods. This report presents a technique for improving the performance of the existing SAT-based combinational equivalence checkers by adding new constraints based on the structural similarity. O...

This paper presents a proposal based on binary particle swarm optimization to design combinational logic circuits at the gate-level. The algorithm is validated using several examples from the literature, and is compared against a genetic algorithm (with integer representation), and against human designers who used traditional circuit design aids (e.g., Karnaugh Maps). Results indicate that part...

The synthesis of fluorescent unnatural amino-acid Anap was optimized and the Anap was incorporated into four sites in an acid-pocket or a transmembrane region of human acid-sensing ion channel-1a (hASIC1a). Combinational Anap fluorescence spectra and patch-clamp electrophysiology data illustrated site-specific conformational responses upon toxin mambalgin-1 binding. This combinational approach ...