The amount of spill code generated by a compiler backend has crucial effects on program performance. Instruction scheduling before register allocation may cause live range overlaps that lead to suboptimal spill code. Even when a local scheduler tries to minimize register usage, its results can leave room for improvement regarding overall spill costs. We present Register Reuse Scheduling (RRS), ...

Value prediction (VP) is a relatively new technique that increases performance by eliminating true data dependency constraints. VP architectures allow data dependent instructions to issue and execute speculatively using the predicted value. This technique is built on the concept of value locality, which describes the likelihood of a previously seen value recurring within a storage location. The...

The paper examines a simple conceptual modification of the operation unit of a RISC processor. We propose to substitute a part of the conventional general purpose register file by a shift register for all operation results. The presented approach allows to reduce the instruction size for a great deal of instructions and so the instruction stream, and it is also a promising approach to make the ...

When modern processors keep increasing the instruction window size and the issue width to exploit more instruction-level parallelism (ILP), the demand of larger physical register file is also on the increase. As a result, register file access time represents one of the critical delays and can easily become a bottleneck. In this paper, we first discuss the possibilities of reducing register pres...

Register allocation in loops is generally performed after or during the software pipelining process. This is because doing a conventional register allocation as a first step without assuming a schedule lacks the information of interferences between values live ranges. Thus, the register allocator may introduce an excessive amount of false dependences that dramatically reduce the ILP (Instructio...

Abstrac t . Graph coloring is the dominant paradigm for global register allocation [8, 7, 4]. Coloring allocators use an interference graph, Z, to model conflicts that prevent two values from sharing a register. Nodes in 2: represent live ranges. An edge between two nodes indicates that they are simultaneously live azld, thus, cannot share a register. The allocator tries to construct a k-colori...

Though it is common practice to treat synchronization primitives for multiprocessors as abstract data types, they are in reality machine instructions on registers. A crucial theoretical question with practical implications is the relationship between the size of the register and its computational power. We wish to study this question and choose as a rst target the popular compare&swap operation...