Floating-gate analog circuits are being used to implement advanced signal processing functions and are very useful for processing analog signals prior to analog to digital conversion. We present an architecture analogous to FPGA architectures for rapid prototyping of analog signal processing systems. These systems go beyond simple programmable amplifiers and filters to include programmable and ...

The architecture for very-high speed DAC with medium oversampling and high resolution is discussed. The scheme uses an hybrid sigma-delta scheme that processes LSBs of the input word and obtain digital to analog conversion with an hybrid current steering DAC with dynamic element matching of MSBs and time interleaved conversion of LSBs. The return-to-zero for all elements ensures the required li...

As device size scales down, there have been challenges to design conventional analog circuits, such as low voltage headroom and the low intrinsic gain of a device. Although ever-decreasing device channel length in CMOS technology has mainly negative effects on analog circuits, it increases device speed and reduces the power consumption of digital circuits. As a result, time-based signal process...

This article presents a new clock-less analog-to-digital converter (ADC) based on a full analog signal processing. The main innovative feature of the proposed ADC is that, for a sampled input signal, a cascade of identical stages may operate without timing signal (clock) with its analog processing independent of the output digital signal’s generation. Clock-less converters are used in the medic...

2.6. Hardware Requirements 2.2.1. Sample-and-hold 2.2.2. Analog-to-digital conversion 2.2.3. ADC resolution and error sources Sampling Rates and Timing Quantisation Errors Signal Overflow 2.5.

Hybrid filter bank analog-to-digital converters (ADCs) have been proposed as a candidate for high-speed, high-resolution analog-to-digital conversion. It is a generalization from time-interleaved ADCs, but it has the advantage that the mismatch errors inherent in parallel converters are attenuated by the filters. This paper gives an overview of hybrid filter bank ADC analysis and design. Furthe...

We outline a methodology for system level test composition out of module level tests in the context of SOC’s. The method can be utilized as soon as high level specifications are available providing avenues for testability insertion. The digital/analog interface is handled by a conversion from digital bits to analog signals. Experimental results show that high fault and yield coverages for most ...

This paper proposes a pipeline analog-to-digital converter (ADC) with non-binary encoding technique based on β-expansion. By using multiply-by-β switched-capacitor (SC) multiplying digital-to-analog converter (MDAC) circuit, our proposed ADC is composed by radix-β (1 < β < 2) 1 bit pipeline stages instead of using the conventional radix-2 1.5 bit/1 bit pipeline stages to realize non-binary anal...

A flexible, reconfigurable receiver architecture that extends the direct conversion architecture is presented. The receiver structure is based on high dynamic range/lowpower Σ∆ analog-to-digital converters (ADC) and digital signal processing functions implemented locally on the radio frequency integrated circuit (RFIC). This relaxes requirements for the analog part of the receiver and enables c...