A 2-GHz direct digital frequency synthesizer (DDFS) chip-set is presented which operates at a very low supply voltage of 2 V. The chip-set consists of a CMOS DDFS-large scale integrator (LSI) which synthesizes a sine wave at 55 Msps with an internal 10-b digital-to-analog converter (DAC) and Si-bipolar image-reject up-converters. To achieve both high purity and low power dissipation, we develop...

We propose an electrostatically-actuated microelectromechanical digital-to-analog converter (M-DAC) device with low actuation voltage. The spring structures of the silicon-based M-DAC device were monolithically fabricated using parylene-C. Because the Young's modulus of parylene-C is considerably lower than that of silicon, the electrostatic microactuators in the proposed device require much lo...

A 9-bit 11GS/s current-steering (CS) digital-to-analog converter (DAC) is designed in 28nm FDSOI. The DAC uses two-times interleaving to suppress the effects of the main error mechanisms of CS DACs while its clock timing can be tuned by the back gates bias voltage of the multiplexer transistors. The DAC achieves higher than 50dB SFDR and less than -50dBc IM3 over Nyquist at a sampling rate of 1...

This paper presents a new approach to static parameters testing of analog-to-digital converters (ADCs). In comparison to ordinary approaches, the measured transition levels are not related to zero potential but to the transition levels of a reference ADC, which is of the same type as a tested ADC. These differences, which can be in the extreme case in the range of a few least significant bits (...

This paper proposes a new DAC BIST (digital-to-analog converter built-in self-test) structure using a resistor loop known as a DDEM ADC (deterministic dynamic element matching analog-to-digital converter). Methods for both switch reduction and switch effect reduction are proposed for solving problems related to area overhead and accuracy of the conventional DAC BIST. The proposed BIST modifies ...

An ultra-wideband (UWB) software defined radio (SDR) implementation is presented. The developed impulse radio (IR) transceiver employs first order bandpass (BP) sampling at a conversion frequency which is four times the channel bandwidth. The subsampling architecture directly provides the RF signal avoiding any non-ideal mixer stages and reduces the requirements of digital signal processing imp...

Due to great value of the time constant of the integrator circuit, a hardware defined PWM (Pulse Width Modulation) signal makes it possible to build a Digital to Analog Converter (DAC) characterized by a relatively long response time. An attempt at creating the software defined PWM signal leads to increased response time of the DAC converter with a coefficient several hundred times longer than ...