Skyrmion-based devices are promising candidates for non-volatile memory and low-delay time computation. Many skyrmion-based execute operation by controlling skyrmion trajectory, which can be impeded the Hall effect. Here, design of arithmetic built on synthetic antiferromagnetic (SyAF) structures is presented, where structure greatly suppress In this study, operations half adder, full XOR logic...

A parallel adder which is optimal in both delay and size under left-to-right input arrival is proposed. The delay is the computation time after the arrival of the nal input bits. The proposed adder is composed of a carry select adder (CSA) and a small adder based on the on-they conversion (OTFA). Parallel computation in the CSA and the OTFA which make full use of the delay of the input arrival ...

Quantum-dot cellular automata (QCA) are a promising nanotechnology to implement digital circuits at the nanoscale. Devices based on QCA have the advantages of faster speed, lower power consumption, and greatly reduced sizes. In this paper, we are presented the circuits, which generate random numbers in QCA.  Random numbers have many uses in science, art, statistics, cryptography, gaming, gambli...

The Full Adder circuit is an important component in application such as Digital Signal Processing (DSP) architecture, microprocessor, and microcontroller and data processing units. This paper discusses the evolution of full adder circuits in terms of lesser power consumption, higher speed. Starting with the most conventional 28 transistor full adder and then gradually studied full adders consis...

Conservative and reversible logic gates are widely known to be compatible with revolutionary computing paradigms such as optical and quantum computing. A fundamental conservative reversible logic gate is the Fredkin gate. This paper presents efficient adder circuits based on the Fredkin gate. Novel full adder circuits using Fredkin gates are proposed which have lower hardware complexity than th...

In this paper, five new multiplexer-based architectures for 1 -bit full adder circuit designs are proposed. Following these architectures, various full adder circuits can be built through different circuit implementations of multiplexers. For instance, in this paper, we demonstrate that by substituting each multiplexer with two transmission gates, a set of new full adder circuits are ready to b...

Parallel-prefix adders (also known as carrytree adders) are known to have the best performance in VLSI designs compared to that of conventional Ripple Carry Adder (RCA). However, each type of parallel prefix adder has its own pros and cons and are chosen according to the design requirement of the application. This paper investigates mainly two types of carry-tree adders, the brent kungg adder a...

Quantum addition circuits are considered being of two types: (1) Toffoli-adder which use only classical reversible gates (controlled-not and Toffoli), (2) QFT-adder based on the quantum Fourier transformation. We present a systematic translation QFT circuit into Toffoli-based adder. This result shows that has fundamentally same fault-tolerance cost (e.g., T count) as most cost-efficient Toffoli...

   Quantum-dot Cellular Automata (QCA) technology is a solution for implementation of the nanometer sized circuits and it can be a suitable replacement for CMOS. Similar to CMOS technology, designing the basic computational element such as adder with the QCA technology is regarded as one of the most important issues that extensive researches have been done about it. In this paper, a new eff...

The objective of the paper is to reduce the hardware complexity of higher order FIR filter with symmetric coefficients. The aim is to design an efficient Fast Finite-Impulse Response (FIR) Algorithms (FFAs) for parallel FIR filter structure, with a constrain that the filter tap must be multiple of 2. In our work we have briefly discussed for L=4 parallel implementation. The parallel FIR filter ...