For meeting the real-time fault diagnosis and the optimization monitoring requirements of the polymerization kettle in the polyvinyl chloride resin (PVC) production process, a fault diagnosis strategy based on the self-organizing map (SOM) neural network is proposed. Firstly, a mapping between the polymerization process data and the fault pattern is established by analyzing the production techn...

The reliability analysis of critical systems can be performed using fault tree analysis. One of the common approaches used for fault tree analysis is Monte Carlo simulation. The purpose of this paper is therefore to show an algorithm to speed up Monte Carlo simulation for analyzing fault tree with parallel computing in GPU. To this end, we use time-to-failure tree to model fault tree with Compu...

This paper describes a feasibility study of accelerating fault simulation by emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. In order to further speed up simulation, we propose to make use of reconfigurable hardware by emulating circuit together with fault insertion structures on FPGA. Exper...

This paper presents the application of radial basis neural networks to the development of a novel method for the condition monitoring and fault diagnosis of synchronous generators. In the proposed scheme, flux linkage analysis is used to reach a decision. Probabilistic neural network (PNN) and discrete wavelet transform (DWT) are used in design of fault diagnosis system. PNN as main part of thi...

Microgrids have played an important role in distribution networks during recent years.  DC microgrids are very popular among researchers because of their benefits. Protection is one of the significant challenges in the way of microgrids progress. As a result, in this paper, a fault detection and location scheme for DC microgrids is proposed. Due to advances in Artificial Intelligence (AI) and s...

The development of a systematic fault-tree synthesis procedure for the override control systems is presented in this paper. The unique configuration of the digraph model under study is first described and then analyzed in detail. On the basis of qualitative simulation of the fault propagation patterns, the corresponding generalized fault-tree structures are then established. It can be observed ...

In this paper, a simple behavior-level fault model, which is able to represent the faulty behavior of the closed-loop operational amplifier (OP), is presented. The fault model, derived from the macro equivalent circuit of the OP but verified with transistor level simulation, consists of the offset fault and the limited-current fault. It can represent the faulty behavior of the closed loop OP of...

We present an evaluation of accelerating fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. In order to evaluate possible simulation speed possibilities, we made a feasibility study of using reconfigurable hardware by emulating circuit under analysis together with f...

A new fault list reduction approach is proposed for use in the first stage of a two-stage bridge fault diagnosis procedure. Modified structural analysis and layout extraction procedures are performed to obtain a reduced realistic bridge fault list that can be used in the second stage, which employs diagnostic fault simulation. The fault list reduction approach can reduce the final candidate bri...