When designing a VLSI circuits, most of the efforts are now performed at levels of abstractions higher than gate. Correspondingly to this clear trend, there is a growing request to tackle safety-critical issues directly at the RT-level. This paper presents a complete environment for considering safety issues at the RT level. The environment was implemented and tested by an industry for devising...

We analyze the latency of fault-tolerant quantum computing based on the 9-qubit Bacon-Shor code using a local, two-dimensional architecture. We embed the data qubits in a 7 by 7 array of physical qubits, where the extra qubits are used for ancilla preparation and qubit transportation by means of a SWAP chain. The latency is reduced with respect to a similar implementation using Steane’s 7-qubit...

We present a Built-In Self-Test (BIST)-based diagnostic approach for the programmable interconnect resources in Field Programmable Gate Arrays (FPGAs) that can be used for either on-line or off-line testing. The technique was originally intended for on-line diagnosis of faulty interconnect to support fault-tolerant applications. However, the technique has been proven to be an excellent approach...

A new Fault Tolerant Controller (FTC) has been presented in this research by integrating a Fault Detection and Diagnosis (FDD) mechanism in a nonlinear model predictive controller framework. The proposed FDD utilizes a Multi-Sensor Data Fusion (MSDF) methodology to enhance its reliability and estimation accuracy. An augmented state-vector model is developed to incorporate the occurred senso...

In this paper we introduce a new interconnection network Fault Tolerant Hierarchical Interconnection network for parallel Computers denoted by FTH(k, 1).This network has fault tolerant hierarchical structure which overcomes the fault tolerant properties of Extended hypercube(EH).This network has low diameter, constant degree connectivity and low message traffic density in comparisons with other...

We describe in detail a general strategy for implementing a conditional geometric phase between two spins. Combined with single-spin operations, this simple operation is a universal gate for quantum computation, in that any unitary transformation can be implemented with arbitrary precision using only single-spin operations and conditional phase shifts. Thus quantum geometrical phases can form t...

We implement all single-qubit operations with fidelities significantly above the minimum threshold required for fault-tolerant quantum computing, using a trapped-ion qubit stored in hyperfine "atomic clock" states of ^{43}Ca^{+}. We measure a combined qubit state preparation and single-shot readout fidelity of 99.93%, a memory coherence time of T_{2}^{*}=50  sec, and an average single-qubit gat...

In this paper we show how the fault–tolerant error correction scheme recently proposed by DiVincenzo and Shor may be improved. Our scheme, unlike the earlier one, can also deal with a single error that might occur during the gate operations that are required for the implementation of the error correction and not only in–between the gates and hence presents an improvement towards enabling error ...

Advances in VLSI technology have led to fabrication of chips with number of transistors projected to reach 10 billion in the near future. Affordable fault tolerant solutions transparent to applications with minimal hardware overhead in the micro architecture are necessary to mitigate component level errors for emerging system-on-chip (SoC) platforms. Ridgetop Group and the University of Arizona...