Network-on-Chip (NoC) is most widely used as a communication framework to connect various Intellectual Properties (IPs) in an Integrated Circuit (IC). As technology scales down, buffers present NoC Router are more prone Multiple Cell Upsets (MCUs). To overcome this, Error Correction Code (ECC) introduced Router. Inclusion of ECC increases the number redundant bits stored buffer for error correc...

As chip complexity keeps increasing in system-on-chip (SoC), the on-chip interconnect has become a critical issue for large-scale chip design. It has been proposed that the packet-switched network exchanging messages between intellectual property (IP) cores is a viable solution for the SoC interconnect problem. The design of the router in such network-on-chip (NoC) architectures is the key to h...

This paper applies programming language techniques to a high-level system description, both to optimize the system and to prove useful properties about it. The system in question is Click, a modular software router framework [13]. Click routers are built from components called elements. Elements are written in C++, but the user creates a configuration using a simple, declarative data flow langu...

Fast Mobile IPv6 requires that a Fast Binding Update is secured using a security association shared between an Access Router and a Mobile Node in order to avoid certain attacks. In this document, a method for provisioning a shared key from the Access Router to the Mobile Node is defined to protect this signaling. The Mobile Node generates a public/private key pair using the same public key algo...

Purpose: The present systematic review and meta-analysis aims to investigate the role of posterior tibial nerve stimulation (PTNS) in the control of fecal incontinence (FI). Methods: Two independent reviewers extensively searched in the electronic databases of Medline, Embase, Cochrane Central Register of Controlled Trials (CENTRAL), Web of Science, CINAHL, and Scopus for the studies published...

Chip Multi-Processor (CMP) architectures have become mainstream for designing processors. With a large number of cores, Network-On-Chip (NOC) provides a scalable communication method for CMP architectures, where wires become abundant resources available inside the chip. NOC must be carefully designed to meet constraints of power and area, and provide ultra low latencies. In this paper, we propo...

In the last decade many works has been done on the Internet topology at router or autonomous system (AS) level. As routers is the essential composition of ASes while ASes dominate the behavior of their routers. It is no doubt that identifying the affiliation between routers and ASes can let us gain a deeper understanding on the topology. However, the existing methods that assign a router to an ...