In this paper, we present new Boolean matching methods for lookup table (LUT)-based programmable logic blocks (PLBs) and their applications to PLB architecture evaluations and field programmable gate array (FPGA) technology mapping. Our Boolean matching methods, which are based on functional decomposition operations, can characterize functions for complex PLBs consisting of multiple LUTs (possi...

|Programmable Active Memories (PAM) are a novel form of universal recon gurable hardware co-processor. Based on Field-Programmable Gate Array (FPGA) technology, a PAM is a virtual machine, controlled by a standard microprocessor, which can be dynamically and inde nitely recongured into a large number of application-speci c circuits. PAMs o er a new mixture of hardware performance and software v...

Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional description of the circuit, with no timing consideration. On the other hand, simulation runs mainly on subsets of the entire input domain. Furthermore, these tools provide results in a format (e.g. state graphs, bit ve...

In this paper we present a novel RAM-based field programmable mixedsignal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core. This processor can run general purpose user programs, handle the dynamic reconfiguration of the programmable blocks and probe in real time internal digital and analog ...

This paper describes a new reconfigurable analog array (RAA) architecture and integrated circuit (IC) used to map analog circuits that can adapt to extreme temperatures under programmable control. Algorithmdriven adaptation takes place on the RAA IC. The algorithms are implemented in a separate Field Programmable Gate Array (FPGA) IC, co-located with the RAA in the extreme temperature environme...

Field-programmable gate array (FPGA) technology represents a potential alternative to classical CPUs and GPUs in the post-Moore era from edge computing data centers [...]

The main idea and procedure are presented for a new synthetical method on constraining 3-D structure of emission regions of pulsars. With this method the emission regions can be synthetically constrained by fitting multi-wavelength observations features, e.g. pulse widths, phase offsets between radio pulse profiles and high energy light curves, and radio polarization properties. The main techni...

We present the design-scheme and physical implementation for a Dynamic Adaptive Neural Network Array (DANNA) based upon the work by Schuman and Birdwell [1,2] and using a programmable array of elements constructed with a Field Programmable Gate Array (FPGA). The aim of this paper is to demonstrate how a single programmable neuromorphic element can be designed to support the primary components o...

Efficient implementation of double point multiplication is crucial for elliptic curve cryptographic systems. We revisit three recently proposed simultaneous double point multiplication algorithms. We propose hardware architectures for these algorithms, and provide a comparative analysis of their performance. We implement the proposed architectures on Xilinx Virtex-4 FPGA, and report on the area...

Today, real-time processing has become a stipulation in all practical fields especially in image processing. This paper presents an experimental comparison of implementation of Niblack’s Algorithm, a binarization algorithm for image-processing in Visual C++ using OpenCV library with its implementation on FPGA. It aims at addressing the real-time processing scenario and how to overcome the situa...