Soft error performance of 16-nm designs fabricated using a commercial bulk C evaluated using heavy-ions. Results included variations show that multi-cell upsets dominate Dual-port SRAM has higher cross-section SRAM but did not have any multi-cell upset a direction. TCAD simulations showing the perturbation in the electric parameters as a fu LET support the experimental data. KeywordsSRAM, FinFE...

For the first time, we analyse SRAM cells made of ferroelectric based negative capacitance (NC) FinFETs considering both global and local variability via Monte-Carlo circuit simulations. First compare explain impact on device characteristics extracted figures merit conventional NC transistors. Then show that suppressed relative in NCFETs leads to lowering static Vmin (minimum supply voltage nee...

For the first time, we analyse SRAM cells made of ferroelectric based negative capacitance (NC) FinFETs considering both global and local variability via Monte-Carlo circuit simulations. First compare explain impact on device characteristics extracted figures merit conventional NC transistors. Then show that suppressed relative in NCFETs leads to lowering static Vmin (minimum supply voltage nee...

Article history: Received 13 May 2013 Received in revised form 3 October 2015 Accepted 26 November 2015 Available online xxxx This paper proposes a new ultra-low leakage, single-ended FinFET-based SRAM cell to improve the stability and read ON/OFF current ratio. The design employs a power gate transistor that shares the read path and main body current to improve the cell stability (SNM) by refo...

The biosensor design for sensing of biological signals is highly complex for accurate detection. Optimal detection of biological signals is necessary for distinguishing different tissues. This paper proposes a threshold-based detection technique which provides significant improvement in FinFET optical biosensor performance using wavelet coefficients. It uses a simple maximum likelihood (ML) fun...

The growth of battery-powered mobile and wearable devices has increased the importance of low-power operation and cost in system-on-a-chip (SoC) design. Supply-voltage scaling is the predominant approach to active power reduction for SoC design, including voltage scaling for on-die memory given increasing levels of memory integration. SRAM can limit the minimum operating voltage (VMIN) of a des...

In this paper, a hybrid memory architecture based on new array of SRAM and resistive random-access (RRAM) cells is proposed to perform in-memory computing by implementing all basic two-input Boolean functions. The can be configured as dual-purpose element. It used an in mode keep data for high-performance application requirements. also sense amplifier (SA-SRAM) reading the contents RRAMs perfor...

Present complementary metal–oxide–semiconductor (CMOS) technology with scaled channel lengths exhibits higher energy consumption in designing secure electronic circuits against hardware vulnerabilities and breaches. Specifically, CMOS sense amplifier-based differential power analysis (DPA) countermeasures at show large consumption, increased vulnerability. Additionally, spin-transfer torque mag...

Advancement in the semiconductor industry has transformed modern society. A miniaturization of a silicon transistor is continuing following Moore?s empirical law. The planar metal-oxide field effect (MOSFET) structure reached its limit terms technological node reduction. To ensure continuation CMOS scaling and to overcome Short Channel Effect (SCE) issues, new MOS known as Fin field-effect (Fin...