Substrate noise effects caused by the integration of a DC-DC converter into a 0.13 μm CMOS technology integrated circuit are investigated in this paper. Simulations performed using the Substrate Noise Analyst tool show strong impact of switching and power supply noise on a sensitive analog block. The dependence of substrate noise coupling on physical separation distance, floorplanning and intro...

The macro placement is a governing factor in design flow in terms of timing criticality and congestion metrics. Also tape-out schedules are affected because of quality of macro placement or floorplanning. As hierarchical approach is followed for design closure today, there are multiple macro iterations back and forth between synthesis and implementation tool until the design meet all timing and...

Level of knowledge with the field for VLSI IC Design’s Placement and Routing in area Wireless Communication is rapidly evolving; Hence process designing above fields critical to assimilate a higher quantity computation elements or nodes into very compact size Area also same applicable Communications cover more number specific area. Prior completing placement, physical technical arranging chip p...

Given a finite nonincreasing sequence of positive numbers a1 ≥ a2 ≥ . . . ≥ an > 0, select index j such that the absolute value of the difference between the sum of the first j terms and the sum of the remaining n− j terms is minimized. An analysis shows that the ratio of these two sums is then bounded between γ ≡ max{2, β} and 1/γ, where β is the maximum pairwise ratio of successive terms in t...

Although rectangular dualization has been studied for several years in the context of floorplanning problems, its descriptive power has not been fully exploited for graph representation. The main obstacle is that the computation of a rectangular dual of any planar biconnected graph requires a sequence of non-trivial steps, some of which are still under investigation. In particular, the most tri...

This paper presents research to address the temperature challenge in multicore processors through the lever of thermally-aware floorplanning. Specifically, it examines the thermal benefit in a variety of placement choices available in a multicore processor including alternative core orientation and insertion of L2 cache banks between cores as cooling buffers. In comparison with an idealized sch...

The context for partitioning in physical design is dominated by two concerns: top-down design and the focus on spatial embedding. The role of partitioning is exactly that of a facilitator of divide-and-conquer metaheuristics for floorplanning, timing and placement optimization. Formulations or optimization objectives for partitioning follow from its context and role. Finally, the available algo...

We propose fresher looks into already existing hierarchical partitioning based floorplan design methods and their relevance in providing faster alternatives to conventional approaches. We modify the existing partitioning based floorplanner to handle congestion and timing. We also explore the applicability of traditional Sizing Theorem for combining two modules based on their sizes and interconn...